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ADC71JG Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADC71JG
Beschreibung 16-Bit ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 9 Seiten
ADC71JG Datasheet, Funktion
® ADC71
16-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 16-BIT RESOLUTION
q ±0.003% MAXIMUM NONLINEARITY
q COMPACT DESIGN: 32-pin Hermetic
Ceramic Package
q CONVERSION SPEED: 50µs max
DESCRIPTION
The ADC71 is a low cost, high quality, 16-bit succes-
sive approximation analog-to-digital converter. It uses
laser-trimmed ICs and is packaged in a convenient
32-pin hermetic ceramic dual-in-line package. The
converter is complete with internal reference, clock,
comparator, and thin-film scaling resistors, which
allow selection of analog input ranges of ±2.5V, ±5V,
±10V, 0 to +5V, 0 to +10V and 0 to +20V.
Data is available in parallel and serial form with
corresponding clock and status output. All digital in-
puts and outputs are TTL-compatible.
Power supply voltages are ±15VDC and +5VDC.
Parallel
Digital
Output
Short Cycle
Convert Command
16-Bit
Successive Approx.
Register (SAR)
16-Bit D/A
Converter
Reference
Ref Out (+6.3V)
}Input Range
Select
Comparator In
Clock
Clock Out
Status
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1990 Burr-Brown Corporation
PDS-1060A
Printed in U.S.A. December, 1993






ADC71JG Datasheet, Funktion
MSB
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Dotted Lines
Are External
Connections
ADC71
32 0.01µF(1)
31
30 270k
29
28
27
26 Bipolar
Offset
25
1.8M
24
23 NC
22
21
20
19
18
17 NC
Convert Command From
Control Logic
Gain
Adjust
10kto
100k
Status Output to
Control Logic
+
Offset
Adjust
+
1µF
10kto
100k
+ 1µF
1µF
Digital
Common
+5VDC
+15VDC
Analog Input
±10V
–15VDC
Analog
Common
NOTE: (1) Capacitor should be connected even if external gain adjust is not used.
FIGURE 5. ADC71 Connections for: ±10V Analog Input, 14-Bit Resolution (Short-Cycled), Parallel Data Output.
SERIAL DATA
Two straight binary (complementary) codes are available on
the serial output line: CSB and COB. The serial data is
available only during conversion and appears with MSB
occurring first. The serial data is synchronous with the
internal clock as shown in the timing diagrams of Figures 2
and 3. The LSB and transition values shown in Table I also
apply to the serial data output except for the CTC code.
DISCUSSION
OF SPECIFICATIONS
The ADC71 is specified to provide critical performance
criteria for a wide variety of applications. The most critical
specifications for an A/D converter are linearity, drift, gain
and offset errors. This ADC is factory-trimmed and tested
for all critical key specifications.
(a)
27
Comparator In
1.8M
(b)
27 180k
Comparator In
180k
22k
+15VDC
10kto 100k
Offset Adjust
–15VDC
+15VDC
10kto 100k
Offset Adjust
–15VDC
FIGURE 6. Two Methods of Connecting Optional Offset
Adjust with a 0.4% of FSR of Adjustment.
GAIN AND OFFSET ERROR
Initial Gain and Offset errors are factory-trimmed to typi-
cally ±0.1% of FSR (typically ±0.05% for unipolar offset) at
25°C. These errors may be trimmed to zero by connecting
external trim potentiometers as shown in Figures 6 and 7.
POWER SUPPLY SENSITIVITY
Changes in the DC power supplies will affect accuracy. The
power supply sensitivity is specified for ±0.003% of FSR/
%VS for ±15V supplies and ±0.001% of FSR/%S for +5
supplies. Normally, regulated power supplies with 1% or
less ripple are recommended for use with this ADC. See
Layout Precautions, Power Supply Decoupling and Figure
8.
29
Gain Adjust
22
Analog Common
270k
0.01µF
+15VDC
10kto 100k
Gain Adjust
–15VDC
FIGURE 7. Connecting Optional Gain Adjust with a 0.2%
Range of Adjustment.
®
ADC71
6

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