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ADC700JH Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADC700JH
Beschreibung 16-Bit Resolution With Microprocessor Interface A/D CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 12 Seiten
ADC700JH Datasheet, Funktion
® ADC700
16-Bit Resolution With Microprocessor Interface
A/D CONVERTER
FEATURES
q COMPLETE WITH REFERENCE, CLOCK,
8-BIT PORT MICROPROCESSOR
INTERFACE
q CONVERSION TIME: 17µs max
q LINEARITY ERROR: ±0.003% FSR max
q NO MISSING CODES TO 14 BITS OVER
TEMPERATURE
q SPECIFIED AT ±12V AND ±15V SUPPLIES
q OUTPUT BUFFER LATCH FOR IMPROVED
INTERFACE TIMING FLEXIBILITY
q PARALLEL AND SERIAL DATA OUTPUT
q SMALL PACKAGE: 28-Pin DIP
DESCRIPTION
The ADC700 is a complete 16-bit resolution succes-
sive approximation analog-to-digital converter.
The reference circuit, containing a buried zener, is
laser-trimmed for minimum temperature coefficient.
The clock oscillator is current-controlled for excellent
stability over temperature. Gain and Zero errors may
be externally trimmed to zero. Analog input ranges of
0V to +5V, 0V to +10V, 0V to +20V, ±2.5V, ±5V, and
±10V are available.
The conversion time is 17µs max for a 16-bit conver-
sion over the three specification temperature ranges.
After a conversion, output data is stored in a latch
separate from the successive approximation logic. This
permits reading data during the next conversion, a
feature that provides flexible interface timing, espe-
cially for interrupt-driven interfaces.
Data is available in two 8-bit bytes from TTL-compat-
ible three-state output drivers. Output data is coded in
Straight Binary for unipolar input signals and Bipolar
Offset Binary or Twos complement for bipolar input
signals. BOB or BTC is selected by a logic function
available on one of the pins.
The ADC700 is available in commercial, industrial
and military temperature ranges. It is packaged in a
hermetic 28-pin side-braze ceramic DIP.
Data
Serial Data
Ready Status Strobe
Serial Data
CS
RD
WR
HBEN
BTCEN
Reset
10V
Analog
Inputs
20V
SJ
Clock
and
Control Logic
Bipolar
Offset
Comparator
Successive
Approximation
Register
3-
Data State
16 Latch
3-
State
16-Bit
D/A
Converter
16
Voltage
Reference
8
Parallel
Data
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1989 Burr-Brown Corporation
PDS-856A
Printed in U.S.A. October, 1993






ADC700JH Datasheet, Funktion
TWO’S COMPLEMENT DATA CODE
BTCEN (pin 23) is a logic function that implements the
Binary Two’s Complement output code for bipolar (+ and –)
analog input signal operation. This feature is compatible
with twos complement arithmetic in microprocessor math
algorithms.
INTERNAL CLOCK
The ADC700 has a self-contained clock to sequence the
A/D logic. The clock is not available externally. An external
16-pulse strobe (pin 14) is brought out to clock serial data
only. Use of ADC700 with external clock is not possible.
INTERNAL VOLTAGE REFERENCE
The ADC700 has an internal low-noise buried-zener voltage
reference. The reference circuit has been drift compensated
over the MIL temperature range using a laser trim algorithm.
The reference voltage is not available externally.
DISCUSSION
OF SPECIFICATIONS
BASIC DEFINITIONS
Refer to Figure 3 for an illustration of A/D converter
terminology and to Table II in the Calibration section.
Full Scale Range, FSR
The nominal range of the A/D converter. For ADC700, the
FSR is 20V for the 0V to +20V and the –10V to +10V input
ranges or 10V for the 0V to +10V and –5V to +5V input
ranges.
Least Significant Bit, LSB
The smallest analog input change resolved by the A/D
converter. For an A/D converter with N bits output, the input
value of the LSB is FSR(2–N).
Most Significant Bit, MSB
That binary digit that has the greatest value or weight. The
MSB weight is FSR/2.
Resolution
An N-bit binary-coded A/D converter resolves the analog
input into 2N values represented by the 2N digital output
codes.
ACCURACY
Linearity Error, Integral Linearity Error (ILE)
Linearity Error is defined as the deviation of actual analog
input values from the ideal values about a straight line drawn
through the code mid-points near positive full scale (at +VFS
–1LSB) and at Zero input (at 1/2LSB below the first code
transition, i.e. at Zero) or, in the case of bipolar operation,
near minus full scale (at 1/2LSB below the first code
transition, i.e. at –VFS). Despite the definition, however,
code transitions are easier to measure than code midpoints.
Therefore linearity is measured as the deviation of the
analog input values from a line drawn between the first and
last code transitions. Linearity Error specifications are ex-
pressed in % of Full Scale Range (FSR). ADC700KH ILE
is ±0.003% of FSR which is 1/2 LSB at 14-bits.
Differential Linearity Error (DLE), No Missing Codes
Differential Linearity Error is defined as the deviation in
code width from the ideal value of 1LSB. If the DLE is
greater than –1LSB anywhere along the range, the A/D will
have at least one missing code. ADC700KH is specified to
have a DLE of ±0.006% of FSR, which is ±1LSB at 14 bits.
ADC700KH is specified to have no missing codes at the 14-
bit level over specified temperature ranges.
Gain Error
The deviation from the ideal magnitude of the input span
between the first code midpoint (at –VFS + 1/2LSB, for
bipolar operation; at Zero for unipolar operation) to the last
code midpoint (VFS –1LSB). As with the linearity error
DBN
DBN
5V
3k
3kCL
DGND
A) High-Z to VOH (t3)
and VOL to VOH (t6).
CL
DGND
B) High-Z to VOL (t3)
and VOH to VOL (t6).
FIGURE 1. Load Circuits for Access Time.
DBN
DBN
5V
3k
FFFH
FFEH
FFDH
802H
801H
800H
7FFH
7FEH
002H
001H
000H
Offset Error
Shifts The Line
(Bipolar
Zero
Transition)
Gain
Error
Rotates
The
Line
Midscale
(Bipolar Zero)
3k10pF
10pF
DGND
DGND
A) VOH to High-Z.
B) VOL to High-Z.
FIGURE 2. Load Circuits for Output Float Delay.
®
ADC700
1/2LSB
Zero
(–Full
Scale)
Zero
(–Full-Scale
Calibration
Transition)
1/2LSB
Analog Input
3/2LSB
+Full-Scale
Calibration
Transition
FIGURE 3. Transfer Characteristic Terminology.
6
+Full
Scale

6 Page









ADC700JH pdf, datenblatt
Because the last data-word is stored in the data latch, it is
possible to read it during the next A/D conversion. Assertion
of CS and HBEN for reading parallel data should be timed
from Status going low. The two-byte read operation must be
complete before the conversion in process is complete or the
Data Read is invalid.
Serial Data is available during continuous conversion with
word synchronization available from STATUS.
USING A SAMPLE/HOLD WITH ADC700
Figure 12 illustrates using ADC700 with the Burr-Brown
SHC76. The sample-to-hold settling time (to 14 bits,
±0.003%FSR) of the SHC76 is 1µs typ, 3µs max. The time
from the Status going High to the first conversion decision
is about 900ns. Therefore a time delay between the Sample-
to-Hold command to the WR command to the ADC700 is
required.
Analog
In
SHC76
ADC700
Sample
Mode
Control
ADC700
WR
Mode
Control
Hold
1µs to 3µs
Start Conversion
FIGURE 12. Using Sample/Hold with ADC700 Requires
Time Delay Between Sample and Start-of-Con-
version.
®
ADC700
12

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