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PDF ADC16061CCVT Data sheet ( Hoja de datos )
| Número de pieza | ADC16061CCVT | |
| Descripción | Self-Calibrating 16-Bit/ 2.5 MSPS/ 390 mW A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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January 2000
ADC16061
Self-Calibrating 16-Bit, 2.5 MSPS, 390 mW A/D Converter
General Description
The ADC16061 is a self-calibrating 16-bit, 2.5 Megasample
per second analog to digital converter. It operates on a single
+5V supply, consuming just 390mW (typical).
The ADC16061 provides an easy and affordable upgrade
from 12 bit and 14 bit converters. The ADC16061 may also
be used to replace many hybrid converters with a resultant
saving of space, power and cost.
The ADC16061 operates with excellent dynamic perfor-
mance at input frequencies up to 1⁄2 the clock frequency. The
calibration feature of the ADC16061 can be used to get more
consistent and repeatable results over the entire operating
temperature range. On-command self-calibration reduces
many of the effects of temperature-induced drift, resulting in
more repeatable conversions.
The Power Down feature reduces power consumption to
less than 2mW.
The ADC16061 comes in a TQFP and is designed to operate
over the commercial temperature range of 0˚C to +70˚C.
Features
n Single +5V Operation
n Self Calibration
n Power Down Mode
Key Specifications
n Resolution
n Conversion Rate
n DNL
n SNR (fIN = 500 kHz)
n Supply Voltage
n Power Consumption
Applications
n PC-Based Data Acquisition
n Document Scanners
n Digital Copiers
n Film Scanners
n Blood Analyzers
n Sonar/Radar
16 Bits
2.5 Msps (min)
1.0 LSB (typ)
80 dB (typ)
+5V ±5%
390mW (typ)
Connection Diagram
Ordering Information
Commercial
(0˚C ≤ TA ≤ +70˚C)
ADC16061CCVT
DS100889-1
Package
VEG52A 52 Pin Thin Quad Flat Pack
© 2000 National Semiconductor Corporation DS100889
www.national.com
1 page  
Pin Descriptions and Equivalent Circuits (Continued)
Digital Power
20 VD
12,
13,
14,
19,
41,
42, 43
DGND
34 VD I/O
33 DGND I/O
NC
2, 3,
9, 15,
16, 39
NC
Positive digital supply pin. This pin should be connected to the
same clean, quiet +5V source as is VA and bypassed to DGND
with a 0.1 µF monolithic capacitor in parallel with a 10µF capacitor,
both located within 1 cm of the power pin.
The ground return for the digital supply. AGND and DGND should
be connected together directly beneath the ADC16061 package.
See Section 5 (Layout and Grounding) for more details.
Positive digital supply pin for the ADC16061’s output drivers. This
pin should be connected to a +3V to +5V source and bypassed to
DGND I/O with a 0.1 µF monolithic capacitor. If the supply for this
pin is different from the supply used for VA and VD, it should also
be bypassed with a 10 µF capacitor. All bypass capacitors should
be located within 1 cm of the supply pin.
The ground return for the digital supply for the ADC16061’s output
drivers. This pin should be connected to the system digital ground,
but not be connected in close proximity to the ADC16061’s DGND
or AGND pins. See Section 5.0 (Layout and Grounding) for more
details.
All pins marked NC (no connect) should be left floating. Do not
connect the NC pins to ground, power supplies, or any other
potential or signal. These pins are used for test in the
manufacturing process.
5 www.national.com
5 Page 
Specification Definitions
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
APERTURE DELAY is the time required after the falling
edge of the clock for the sampling switch to open. In other
words, for the Track/Hold circuit to go from ’track’ mode into
the ’hold’ mode. The Track/Hold circuit affectively stops cap-
turing the input signal and goes into the ’hold’ mode tAD after
the fall of the clock.
OFFSET ERROR is the difference between the ideal LSB
transition to the actual transition point. The LSB transition
should occur when VIN+ = VIN−.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD
−1.76) / 6.02.
FULL SCALE ERROR is the difference between the input
voltage [(VIN+) − (VIN−)] just causing a transition to positive
full scale and VREF − 1.5 LSB, where VREF is ( VREF+ IN) −
(VREF−IN).
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input. The test
is performed with fIN equal to 100 kHz plus integral multiples
of fCLK. The input frequency at which the output is −3 dB
relative to the low frequency input signal is the full power
bandwidth.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
Timing Diagrams
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dB.
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a line drawn from nega-
tive full scale (1⁄2 LSB below the first code transition) through
positive full scale (the last code transition). The deviation of
any given code from this straight line is measured from the
center of that code value.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output stage. Data for any given sample is
available the Pipeline Delay plus the Output Delay after that
sample is taken. New data is available at every clock cycle,
but the data lags the conversion by the pipeline delay.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SI-
NAD)) is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral com-
ponents below half the clock frequency, including harmonics
but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB or dBc, of the rms total of the first six harmonic
components, to the rms value of the input signal.
TIMING DIAGRAM 1. Output Timing
11
DS100889-15
www.national.com
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