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ADC12L063 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC12L063
Beschreibung 12-Bit/ 62 MSPS/ 354 mW A/D Converter with Internal Sample-and-Hold
Hersteller National Semiconductor
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Gesamt 22 Seiten
ADC12L063 Datasheet, Funktion
November 2002
ADC12L063
12-Bit, 62 MSPS, 354 mW A/D Converter with Internal
Sample-and-Hold
General Description
The ADC12L063 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 62 Megasamples per second (MSPS), mini-
mum. This converter uses a differential, pipelined architec-
ture with digital error correction and an on-chip sample-and-
hold circuit to minimize die size and power consumption
while providing excellent dynamic performance. Operating
on a single 3.3V power supply, this device consumes just
354 mW at 62 MSPS, including the reference current. The
Power Down feature reduces power consumption to just 50
mW.
The differential inputs provide a full scale input swing equal
to ±VREF with the possibility of a single-ended input. Full use
of the differential input is recommended for optimum perfor-
mance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differ-
ential reference for use by the processing circuitry. Output
data format is 12-bit offset binary.
This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
Features
n Single supply operation
n Low power consumption
n Power down mode
n On-chip reference buffer
Key Specifications
n Resolution
n Conversion Rate
n Bandwidth
n DNL
n INL
n SNR
n SFDR
n Data Latency
n Supply Voltage
n Power Consumption, 62 MHz
12 Bits
62 MSPS(min)
170MHz
±0.5 LSB(typ)
±1.0 LSB(typ)
66 dB(typ)
78 dB(typ)
6 Clock Cycles
+3.3V ± 300 mV
354 mW(typ)
Applications
n Ultrasound and Imaging
n Instrumentation
n Cellular Base Stations/Communications Receivers
n Sonar/Radar
n xDSL
n Wireless Local Loops
n Data Acquisition Systems
n DSP Front Ends
Connection Diagram
© 2002 National Semiconductor Corporation DS200263
20026301
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ADC12L063 Datasheet, Funktion
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD= VDR = +3.3V, PD
= 0V, VREF = +1.0V, fCLK = 62 MHz, tr = tf = 2 ns, CL = 20 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX: all
other limits TA = TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical Limits
(Note 10) (Note 10)
Units
(Limits)
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
VD = 3.3V
VIN(0)
Logical “0” Input Voltage
VD = 3.0V
IIN(1)
Logical “1” Input Current
VIN+, VIN− = 3.3V
IIN(0)
Logical “0” Input Current
VIN+, VIN− = 0V
CIN Digital Input Capacitance
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
2.0 V(min)
0.8 V(max)
10 µA
−10 µA
5 pF
VOUT(1)
VOUT(0)
IOZ
+ISC
Logical “1” Output Voltage
Logical “0” Output Voltage
TRI-STATE Output Current
Output Short Circuit Source
Current
IOUT = −0.5 mA
IOUT = 1.6 mA
VOUT = 3.3V
VOUT = 0V
VOUT = 0V
100
−100
2.7
0.4
V(min)
V(max)
nA
nA
−20 mA(min)
−ISC
Output Short Circuit Sink Current
POWER SUPPLY CHARACTERISTICS
VOUT = VDR
20 mA(min)
IA Analog Supply Current
PD Pin = DGND, VREF = 1.0V
PD Pin = VDR
102 140 mA(max)
4 mA
ID Digital Supply Current
IDR Digital Output Supply Current
PD Pin = DGND
PD Pin = VDR, fCLK = 0
PD Pin = DGND, (Note 14)
PD Pin = VDR, fCLK = 0
5.3 7 mA(max)
2 mA
<1 mA(max)
0 mA
Total Power Consumption
PD Pin = DGND, CL = 0 pF (Note 15)
PD Pin = VDR, fCLK = 0
354
50
485
mW
mW
PSRR1 Power Supply Rejection
Rejection of Full-Scale Error with
VA = 3.0V vs 3.6V
58
dB
PSRR2 Power Supply Rejection
SNR Degradation w/10 MHz,
250 mVP-P riding on VA
−53
dB
DYNAMIC CONVERTER CHARACTERISTICS
BW Full Power Bandwidth
0 dBFS Input, Output at −3 dB
170
MHz
SNR
Signal-to-Noise Ratio
fIN = 1 MHz, Differential VIN =
−0.5 dBFS
fIN = 10 MHz, Differential VIN =
−0.5 dBFS
66 dB
66
63.3
dB(min)
SINAD Signal-to-Noise and Distortion
fIN = 1 MHz, Differential VIN =
−0.5 dBFS
fIN = 10 MHz, Differential VIN =
−0.5 dBFS
65
65 62
dB
dB
ENOB Effective Number of Bits
fIN = 1 MHz, Differential VIN =
−0.5 dBFS
fIN = 10 MHz, Differential VIN =
−0.5 dBFS
10.6
10.3
10.0
Bits
Bits
THD
Total Hamonic Distortion
fIN = 1 MHz, Differential VIN =
−0.5 dBFS
fIN = 10 MHz, Differential VIN =
−0.5 dBFS
−80 dB
−74 −65 dB(max)
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ADC12L063 pdf, datenblatt
Typical Performance Characteristics VA = VD = VDR = 3.3V, fCLK = 62MHz, fIN = 10 MHz unless
otherwise stated (Continued)
SNR vs. VA
SNR vs. fCLK
20026364
SNR vs. Clock Duty Clock Cycle
SNR vs. VREF
20026368
20026371
SNR vs. Temperature
THD vs. VA
20026369
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20026370

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