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ADC12762CCV Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC12762CCV
Beschreibung 12-Bit/ 1.4 MHz/ 300 mW A/D Converter with Input Multiplexer and Sample/Hold
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 20 Seiten
ADC12762CCV Datasheet, Funktion
June 1999
ADC12762
12-Bit, 1.4 MHz, 300 mW A/D Converter
with Input Multiplexer and Sample/Hold
General Description
Using an innovative multistep conversion technique, the
12-bit ADC12762 CMOS analog-to-digital converter digitizes
signals at a 1.4 MHz sampling rate while consuming a maxi-
mum of only 300 mW on a single +5V supply. The
ADC12762 performs a 12-bit conversion in three
lower-resolution “flash” conversions, yielding a fast A/D with-
out the cost and power dissipation associated with true flash
approaches.
The analog input voltage to the ADC12762 is tracked and
held by an internal sampling circuit, allowing high frequency
input signals to be accurately digitized without the need for
an external sample-and-hold circuit. The ADC12762 features
two sample-and-hold/flash comparator sections which allow
the converter to acquire one sample while converting the
previous. This pipelining technique increases conversion
speed without sacrificing performance. The multiplexer out-
put is available to the user in order to perform additional ex-
ternal signal processing before the signal is digitized.
When the converter is not digitizing signals, it can be placed
in the Standby mode; typical power consumption in this
mode is 250 µW.
Features
n Built-in sample-and-hold
n Single +5V supply
n Single channel or 2 channel multiplexer operation
Key Specifications
n Sampling rate
n Conversion time
n SNR, fIN= 100 kHz
n Power dissipation (fs= 1.4 MHz)
n No missing codes over temperature
1.4 MHz (min)
593 ns (typ)
67.5 dB (min)
300 mW (max)
Guaranteed
Applications
n CCD image scanners
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
n Waveform digitizers
ADC12762 Block Diagram
Ordering Information
Commercial (0˚C TA +70˚C)
ADC12762CCV
ADC12062EVAL
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS012811
DS012811-1
Package
V44 Plastic Leaded Chip Carrier
Evaluation Board
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ADC12762CCV Datasheet, Funktion
Typical Performance Characteristics (Continued)
Conversion Time (tCONV)
vs Temperature
EOC Delay Time (tEOC)
vs Temperature
Spectral Response
DS012811-12
SINAD vs Input Frequency
(ADC In)
DS012811-13
SNR vs Input Frequency
(ADC In)
DS012811-14
THD vs Input Frequency
(ADC In)
DS012811-15
SINAD vs Input Frequency
(Through Mux)
DS012811-16
SNR vs Input Frequency
(Through Mux)
DS012811-17
THD vs Input Frequency
(Through Mux)
DS012811-18
DS012811-19
DS012811-20
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ADC12762CCV pdf, datenblatt
Applications Information (Continued)
FIGURE 5. The Capacitive Voltage Divider
DS012811-28
DS012811-29
FIGURE 6. ADC Control Logic
THE ANALOG INPUT
The analog input of the ADC12762 can be modeled as two
small resistances in series with the capacitance of the input
hold capacitor (CIN), as shown in Figure 7. The S/H switch is
closed during the Sample period, and open during Hold. The
source has to charge CIN to the input voltage within the
sample period. Note that the source impedance of the input
voltage (RSOURCE) has a direct effect on the time it takes to
charge CIN. If RSOURCE is too large, the voltage across CIN
will not settle to within 0.5 LSBs of VSOURCE before the con-
version begins, and the conversion results will be incorrect.
From a dynamic performance viewpoint, the combination of
RSOURCE, RMUX, RSW, and CIN form a low pass filter. Mini-
mizing RSOURCE will increase the frequency response of the
input stage of the converter.
Typical values for the components shown in Figure 7 are:
RMUX = 100, RSW = 100, and CIN = 25 pF. The settling
time to n bits is:
tSETTLE = (RSOURCE + RMUX + RSW) * CIN * n * ln (2).
The bandwidth of the input circuit is:
f−3dB = 1/(2 * 3.14 * (RSOURCE + RMUX + RSW) * CIN)
The ADC12762 is operated in a pipelined sequence, with
one hold capacitor acquiring the next sample while a conver-
sion is being performed on the voltage stored on the other
hold capacitor. This gives the source over tCONV seconds to
charge the hold capacitor to its final value. At 1.4 MHz, the
settling time must be less than 714 ns. Using the settling
time equation and component values given, the maximum
source impedance that will allow the input to settle to 12 LSB
(n = 13) at full speed is 3 k. To ensure 12 LSB settling over
temperature and device-to-device variation, RSOURCE
should be a maximum of 500when the converter is oper-
ated at full speed.
If the signal source has a high output impedance, its output
should be buffered with an operational amplifier capable of
driving a switched 25 pF/100load. Any ringing or instabili-
ties at the op amp’s output during the sampling period can
result in conversion errors. The LM6361 high speed op amp
is a good choice for this application due to its speed and its
ability to drive large capacitive loads. Figure 8 shows the
LM6361 driving the ADC IN input of an ADC12762. The
100 pF capacitor at the input of the converter absorbs some
of the high frequency transients generated by the S/H
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