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PDF ADC12662CIVF Data sheet ( Hoja de datos )
| Número de pieza | ADC12662CIVF | |
| Descripción | 12-Bit/ 1.5 MHz/ 200 mW A/D Converter with Input Multiplexer and Sample/Hold | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 2001
ADC12662
12-Bit, 1.5 MHz, 200 mW A/D Converter
with Input Multiplexer and Sample/Hold
General Description
Using an innovative multistep conversion technique, the
12-bit ADC12662 CMOS analog-to-digital converter digitizes
signals at a 1.5 MHz sampling rate while consuming a maxi-
mum of only 200 mW on a single +5V supply. The
ADC12662 performs a 12-bit conversion in three
lower-resolution “flash” conversions, yielding a fast A/D with-
out the cost and power dissipation associated with true flash
approaches.
The analog input voltage to the ADC12662 is tracked and
held by an internal sampling circuit, allowing high frequency
input signals to be accurately digitized without the need for
an external sample-and-hold circuit. The ADC12662 features
two sample-and-hold/flash comparator sections which allow
the converter to acquire one sample while converting the
previous. This pipelining technique increases conversion
speed without sacrificing performance. The multiplexer out-
put is available to the user in order to perform additional
external signal processing before the signal is digitized.
When the converter is not digitizing signals, it can be placed
in the Standby mode; typical power consumption in this
mode is 250 µW.
Features
n Built-in sample-and-hold
n Single +5V supply
n Single channel or 2 channel multiplexer operation
n Low Power Standby mode
Key Specifications
n Sampling rate
n Conversion time
n Signal-to-Noise Ratio, fIN= 100 kHz
n Power consumption (fs= 1.5 MHz)
n No missing codes over temperature
1.5 MHz (min)
580 ns (typ)
67.5 dB (min)
200 mW (max)
Guaranteed
Applications
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
n Waveform digitizers
ADC12662 Block Diagram
Ordering Information
Industrial (−40˚C ≤ TA ≤ +85˚)
ADC12662CIV
ADC12662CIVF
01187601
Package
V44 Plastic Leaded Chip Carrier
VGZ44A Plastic Quad Flat Package
© 2001 National Semiconductor Corporation DS011876
www.national.com
1 page  
Dynamic Characteristics (Note 10) (Continued)
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF−(SENSE) = AGND, RS = 25Ω, fIN =
100 kHz, 0 dB from fullscale, and fs = 1.5 MHz, unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to
TMAX; all other limits TA = TJ = +25˚C.
Symbol
Parameter
Conditions
Typ Limit Units
(Note 7)
(Note 8)
(Limit)
SNR
Signal-to-Noise Ratio
(Note 11)
TMIN to TMAX
70 67.5 dB (min)
THD
Total Harmonic Distortion
(Note 12)
TMIN to TMAX
−80 −70 dBc (max)
ENOB
Effective Number of Bits
(Note 13)
TMIN to tMAX
11.3 10.8 Bits (min)
IMD Intermodulation Distortion
fIN = 88.7 kHz, 89.5 kHz
−80
dBc
DC Electrical Characteristics
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF−(SENSE) = AGND, and fs = 1.5 MHz,
unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25˚C.
Symbol
Parameter
Conditions
Typ
Limit
Units
(Note 7)
(Note 8)
(Limit)
VIN(1)
VIN(0)
IIN(1)
IIN(0)
VOUT(1)
VOUT(0)
IOUT
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
Logical “1” Output Voltage
Logical “0” Output Voltage
TRI-STATE® Output
Leakage Current
DVCC = AVCC = +5.5V
DVCC = AVCC = +4.5V
DVCC = AVCC = +4.5V,
IOUT = −360 µA
IOUT = −100 µA
DVCC = AVCC = +4.5V,
IOUT = 1.6 mA
Pins DB0–DB11
0.1
0.1
0.1
2.0
0.8
1.0
1.0
2.4
4.25
0.4
3
V (min)
V (max)
µA (max)
µA (max)
V (min)
V (min)
V (max)
µA (max)
COUT
CIN
DICC
AICC
ISTANDBY
TRI-STATE Output Capacitance
Digital Input Capacitance
DVCC Supply Current
AVCC Supply Current
Standby Current (DICC + AICC)
Pins DB0–DB11
PD = 0V
5 pF
4 pF
2 3 mA (max)
32 37 mA (max)
50 µA
AC Electrical Characteristics
The following specifications apply for DVCC = AVCC = +5V, VREF+(SENSE) = +4.096V, VREF−(SENSE) = AGND, and fs = 1.5 MHz,
unless otherwise specified. Boldface limits apply for TA = TJ from TMIN to TMAX; all other limits TA = TJ = +25˚C.
Symbol
Parameter
Conditions
Typ Limit
Units
(Note 7) (Note 8)
(Limits)
fs
tCONV
Maximum Sampling Rate
(1/tTHROUGHPUT)
Conversion Time
(S/H Low to EOC High)
1.5 MHz (min)
510 ns (min)
580
660 ns (max)
Aperture Delay
tAD (S/H Low to Input Voltage Held)
20 ns
tS/H S/H Pulse Width
5 ns (min)
10
400 ns (max)
tEOC
S/H Low to EOC Low
60 ns (min)
90
126 ns (max)
5 www.national.com
5 Page 
Timing Diagrams (Continued)
01187613
FIGURE 3. CS Setup and Hold Timing for S/H, RD, and OE
11 www.national.com
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ADC12662CIVF.PDF ] | |
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