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ADC1251BIJ Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC1251BIJ
Beschreibung Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 16 Seiten
ADC1251BIJ Datasheet, Funktion
December 1994
ADC1251 Self-Calibrating 12-Bit Plus Sign
A D Converter with Sample-and-Hold
General Description
The ADC1251 is a CMOS 12-bit plus sign successive ap-
proximation analog-to-digital converter On request the
ADC1251 goes through a self-calibration cycle that adjusts
for any zero full scale or linearity errors The ADC1251 also
has the ability to go through an Auto-Zero cycle that cor-
rects the zero error during every conversion
The analog input to the ADC1251 is tracked and held by the
internal circuitry so an external sample-and-hold is not re-
quired The ADC1251 has an S H control input which direct-
ly controls the track-and-hold state of the A D A unipolar
analog input voltage range (0 to a5V) or a bipolar range
(b5V to a5V) can be accommodated with g5V supplies
The 13-bit data result is available on the eight outputs of the
ADC1251 in two bytes high-byte first and sign extended
The digital inputs and outputs are compatible with TTL or
CMOS logic levels
Features
Y Self-calibration provides excellent temperature stability
Y Internal sample-and-hold
Y 8-bit mP DSP interface
Y Bipolar input range with a single a5V reference
Y No missing codes over temperature
Y TTL MOS input output compatible
Key Specifications
Y Resolution
12 bits plus sign
Y Conversion Time
8 ms (max)
Y Sampling Rate
83 kHz (max)
Y Linearity Error
g0 6 LSB (g0 0146%) (max)
Y Zero Error
g1 LSB (max)
Y Full Scale Error
g1 5 LSB (max)
Y Power Consumption g5V
113 mW (max)
Applications
Y Digital signal processing
Y High resolution process control
Y Instrumentation
Simplified Block Diagram
Connection Diagram
Dual-In-Line Package
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 11024
Top View
TL H 11024 – 2
Ordering Information
TL H 11024 – 1
Industrial
Package
(b40 C s TA s a85 C)
ADC1251BIJ
ADC1251CIJ
J24A
Military
Package
(b55 C s TA s a125 C)
ADC1251CMJ
ADC1251CMJ 883
J24A
RRD-B30M115 Printed in U S A






ADC1251BIJ Datasheet, Funktion
Electrical Characteristics (Continued)
TL H 11024 – 7
FIGURE 1b Simplified Error Curve vs Output Code without Auto-Cal or Auto-Zero Cycles
FIGURE 1c Simplified Error Curve vs Output Code after Auto-Cal Cycle
Typical Performance Characteristics
TL H 11024 – 8
Zero Error Change vs
Ambient Temperature
Zero Error vs VREF
Linearity Error vs VREF
TL H 11024 – 9
6

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ADC1251BIJ pdf, datenblatt
2 0 Functional Description (Continued)
A conversion sequence can also be controlled by the S H
and CS inputs Taking CS and S H low starts the acquisition
window for the analog input voltage The rising edge of S H
immediately puts the A D in the hold mode and starts the
conversion Using S H will simplify synchronizing the end of
the acquisition window to other signals which may be nec-
essary in a DSP environment
During a conversion the sampled input voltage is succes-
sively compared to the output of the DAC First the ac-
quired input voltage is compared to analog ground to deter-
mine its polarity The sign bit is set low for positive input
voltages and high for negative Next the MSB of the DAC is
set high with the rest of the bits low If the input voltage is
greater than the output of the DAC then the MSB is left
high otherwise it is set low The next bit is set high making
the output of the DAC three quarters or one quarter of full
scale A comparison is done and if the input is greater than
the new DAC value this bit remains high if the input is less
than the new DAC value the bit is set low This process
continues until each bit has been tested The result is then
stored in the output latch of the ADC1251 Next INT goes
low and EOC goes high to signal the end of the conversion
The result can now be read by taking CS and RD low to
enable the DB0 DB8–DB7 DB12 output buffers The high
byte of data is relayed first on the data bus outputs as
shown below
DB0
DB8
Bit 8
DB1
DB9
Bit 9
DB2 DB3 DB4 DB5 DB6 DB7
DB10 DB11 DB12 DB12 DB12 DB12
Bit 10 MSB Sign Bit Sign Bit Sign Bit Sign Bit
Taking CS and RD low a second time will relay the low byte
of data on the data bus outputs as shown below
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
DB8 DB9 DB10 DB11 DB12 DB12 DB12 DB12
LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
The table in Figure 3 summarizes the effect of the digital
control inputs on the function of the ADC1251 The Test
Mode where RD and S H are high and CS and CAL are
low is used during manufacture to thoroughly check out the
operation of the ADC1251 Care should be taken not to in-
advertently be in this mode since DB2 DB3 DB5 and DB6
become active outputs which may cause data bus conten-
tion
2 2 RESETTING THE A D
The ADC1251 is reset whenever a new conversion is start-
ed by taking CS and WR or S H low If this is done when the
analog input is being sampled or when EOC is low the
Auto-Cal correction factors may be corrupted therefore re-
quiring an Auto-Cal cycle before the next conversion When
using WR or S H without Auto-Zero (AZ e 1) to start a
conversion a new conversion can be restarted only after
EOC has gone high signaling the end of the current conver-
sion When using WR with Auto-Zero (AZ e 0) a new con-
version can be restarted during the first 26 clock periods
after the rising edge of WR (tZ) or after EOC has returned
high without corrupting the Auto-Cal correction factors
The Calibration Cycle cannot be reset once started On
power-up the ADC1251 automatically goes through a Cali-
bration Cycle that takes typically 1399 clock cycles For rea-
sons that will be discussed in Section 3 8 a new calibration
cycle needs to be started after the completion of the auto-
matic one
3 0 Analog Considerations
3 1 REFERENCE VOLTAGE
The voltage applied to the reference input of the converter
defines the voltage span of the analog input (the difference
between VIN and AGND) over which 4095 positive output
codes and 4096 negative output codes exist The A-to-D
can be used in either ratiometric or absolute reference ap-
plications The voltage source driving VREF must have a
very low output impedance and very low noise The circuit in
Figure 4 is an example of a very stable reference that is
appropriate for use with the ADC1251
Digital Control Inputs
CS WR S H RD CAL AZ
A D Function
1 1 1 1 Start Conversion without Auto-Zero
1 1 1 1 Start Conversion synchronous with rising edge of S H without Auto-Zero
11
1 1 Read Conversion Result without Auto-Zero
1 1 1 0 Start Conversion with Auto-Zero
11
1 0 Read Conversion Result with Auto-Zero
1X1X
X Start Calibration Cycle
0 X X 1 0 X Test Mode (DB2 DB3 DB5 and DB6 become active)
FIGURE 3 Function of the A D Control Inputs
12

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