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PDF ADC1251 Data sheet ( Hoja de datos )
| Número de pieza | ADC1251 | |
| Descripción | Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADC1251 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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December 1994
ADC1251 Self-Calibrating 12-Bit Plus Sign
A D Converter with Sample-and-Hold
General Description
The ADC1251 is a CMOS 12-bit plus sign successive ap-
proximation analog-to-digital converter On request the
ADC1251 goes through a self-calibration cycle that adjusts
for any zero full scale or linearity errors The ADC1251 also
has the ability to go through an Auto-Zero cycle that cor-
rects the zero error during every conversion
The analog input to the ADC1251 is tracked and held by the
internal circuitry so an external sample-and-hold is not re-
quired The ADC1251 has an S H control input which direct-
ly controls the track-and-hold state of the A D A unipolar
analog input voltage range (0 to a5V) or a bipolar range
(b5V to a5V) can be accommodated with g5V supplies
The 13-bit data result is available on the eight outputs of the
ADC1251 in two bytes high-byte first and sign extended
The digital inputs and outputs are compatible with TTL or
CMOS logic levels
Features
Y Self-calibration provides excellent temperature stability
Y Internal sample-and-hold
Y 8-bit mP DSP interface
Y Bipolar input range with a single a5V reference
Y No missing codes over temperature
Y TTL MOS input output compatible
Key Specifications
Y Resolution
12 bits plus sign
Y Conversion Time
8 ms (max)
Y Sampling Rate
83 kHz (max)
Y Linearity Error
g0 6 LSB (g0 0146%) (max)
Y Zero Error
g1 LSB (max)
Y Full Scale Error
g1 5 LSB (max)
Y Power Consumption g5V
113 mW (max)
Applications
Y Digital signal processing
Y High resolution process control
Y Instrumentation
Simplified Block Diagram
Connection Diagram
Dual-In-Line Package
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 11024
Top View
TL H 11024 – 2
Ordering Information
TL H 11024 – 1
Industrial
Package
(b40 C s TA s a85 C)
ADC1251BIJ
ADC1251CIJ
J24A
Military
Package
(b55 C s TA s a125 C)
ADC1251CMJ
ADC1251CMJ 883
J24A
RRD-B30M115 Printed in U S A
1 page  
Electrical Characteristics (Continued)
Note 6 Two on-chip diodes are tied to the analog input as shown below Errors in the A D conversion can occur if these diodes are forward biased more than
50 mV This means that if AVCC and DVCC are minimum (4 75 VDC) and Vb is maximum (b4 75 VDC) the analog input full-scale voltage must be s g4 8 VDC
Note 7 A diode exists between AVCC and DVCC as shown below
TL H 11024 – 4
TL H 11024 – 5
To guarantee accuracy it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin
Note 8 Accuracy is guaranteed at fCLK e 3 5 MHz At higher or lower clock frequencies accuracy may degrade See the Typical Performance Characteristics
curves
Note 9 Typicals are at TJ e 25 C and represent most likely parametric norm
Note 10 Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 11 Positive linearity error is defined as the deviation of the analog value expressed in LSBs from the straight line that passes through positive full scale and
zero For negative linearity error the straight line passes through negative full scale and zero (See Figures 1b and 1c )
Note 12 The ADC1251’s self-calibration technique ensures linearity full scale and offset errors as specified but noise inherent in the self-calibration process will
result in a repeatability uncertainty of g0 20 LSB
Note 13 If TA changes then an Auto-Zero or Auto-Cal cycle will have to be re-started See the typical performance characteristic curves
Note 14 After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes
Note 15 When using the WR control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the
end of the interval tA therefore making tA end a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR If the falling edge of the clock
is synchronous to the rising edge of WR then tA will end exactly 6 5 clock periods after the rising edge of WR This does not occur when S H control is used
Note 16 The CAL line must be high before a conversion is started
Note 17 The specifications for these parameters are valid after an Auto-Cal cycle has been completed
Note 18 The ADC1251 reference ladder is composed solely of capacitors
Note 19 A Military RETS Electrical Test Specification is available on request At time of printing the ADC1251CMJ 883 RETS specification complies fully with the
boldface limits in this column
FIGURE 1a Transfer Characteristic
5
TL H 11024 – 6
5 Page 
1 0 Pin Descriptions
DVCC (24)
AVCC (4)
Vb (5)
DGND (12)
AGND (3)
VREF (2)
VIN (1)
CS (10)
RD (23)
WR (7)
S H (11)
CLKIN (8)
CAL (9)
AZ (6)
The digital and analog positive power supply
pins The digital and analog power supply
voltage range of the ADC1251 is a4 5V to
a5 5V To guarantee accuracy it is required
that the AVCC and DVCC be connected to-
gether to the same power supply with sepa-
rate bypass capacitors (10 mF tantalum in
parallel with a 0 1 mF ceramic) at each VCC
pin
The analog negative supply voltage pin Vb
has a range of b4 5V to b5 5V and needs
bypass capacitors of 10 mF tantalum in paral-
lel with a 0 1 mF ceramic
The digital and analog ground pins AGND
and DGND must be connected together ex-
ternally to guarantee accuracy
The reference input voltage pin To maintain
accuracy the voltage at this pin should not
exceed the AVCC or DVCC by more than
50 mV or go below a3 5 VDC
The analog input voltage pin To guarantee
accuracy the voltage at this pin should not
exceed VCC by more than 50 mV or go below
Vb by more than 50 mV
The Chip Select control input This input is
active low and enables the WR RD and S H
functions
The Read control input With both CS and RD
low the TRI-STATE output buffers are en-
abled and the INT output is reset high
The Write control input The conversion is
started on the rising edge of the WR pulse
when CS is low When this control line is
used the end of the analog input voltage ac-
quisition window is internally controlled by the
ADC1251
The sample and hold control input This con-
trol input can also be used to start a conver-
sion With CS low the falling edge of S H
starts the analog input acquisition window
The rising edge of S H ends the acquisition
window and starts a conversion
The external clock input pin The typical clock
frequency range is 500 kHz to 6 0 MHz
The Auto-Calibration control input When
CAL is low the ADC1251 is reset and a cali-
bration cycle is initiated During the calibra-
tion cycle the values of the comparator offset
voltage and the mismatch errors in the ca-
pacitor reference ladder are determined and
stored in RAM These values are used to cor-
rect the errors during a normal cycle of A D
conversion
The Auto-Zero control input With the AZ pin
held low during a conversion the ADC1251
goes into an auto-zero cycle before the actu-
al A D conversion is started This Auto-Zero
cycle corrects for the comparator offset volt-
age The total conversion time (tC) is in-
creased by 26 clock periods when Auto-Zero
is used
EOC (22)
INT (21)
DB0 DB8 –
DB7 DB12
(13 – 20)
The End-of-Conversion control output This
output is low during a conversion or a calibra-
tion cycle
The Interrupt control output This output goes
low when a conversion has been completed
and indicates that the conversion result is
available in the output latches Reading the
result or starting a conversion or calibration
cycle will reset this output high
The TRI-STATE output pins Twelve bit plus
sign output data access is accomplished us-
ing two successive RDs of one byte each
high byte first (DB8 – DB12) The data format
used is two’s complement sign bit extended
with DB12 the sign bit DB11 the MSB and
DB0 the LSB
2 0 Functional Description
The ADC1251 is a 12-bit plus sign A D converter with the
capability of doing Auto-Zero or Auto-Cal routines to mini-
mize zero full-scale and linearity errors It is a successive-
approximation A D converter consisting of a DAC compar-
ator and a successive-approximation register (SAR) Auto-
Zero is an internal calibration sequence that corrects for the
A D’s zero error caused by the comparator’s offset voltage
Auto-Cal is a calibration cycle that not only corrects zero
error but also corrects for full-scale and linearity errors
caused by DAC inaccuracies Auto-Cal minimizes the errors
of the ADC1251 without the need for trimming during its
fabrication An Auto-Cal cycle can restore the accuracy of
the ADC1251 at any time which ensures accuracy over
temperature and time
2 1 DIGITAL INTERFACE
On power up a calibration sequence should be initiated by
pulsing CAL low with CS and S H high To acknowledge the
CAL signal EOC goes low after the falling edge of CAL and
remains low during the calibration cycle of 1399 clock peri-
ods During the calibration sequence first the comparator’s
offset is determined then the capacitive DAC’s mismatch
errors are found Correction factors for these errors are then
stored in internal RAM
A conversion can be initiated by taking CS and WR low If
AZ is low an Auto-Zero cycle which takes approximately 26
clock periods is inserted before the analog input is sampled
and the actual conversion is started AZ must remain low
during the complete conversion sequence After Auto-Zero
the acquisition opens and the analog input is sampled for
approximately 7 clock periods If AZ is high the Auto-Zero
cycle is not inserted after the rising edge of WR In this case
the acquisition window opens when the ADC1251 com-
pletes a conversion signaled by the rising edge of EOC At
the end of the acquisition window EOC goes low signaling
that the analog input is no longer being sampled and that
the A D successive approximation conversion has started
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADC1251.PDF ] | |
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