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ADC12441 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC12441
Beschreibung Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold
Hersteller National Semiconductor
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Gesamt 14 Seiten
ADC12441 Datasheet, Funktion
November 1994
ADC12441 Dynamically-Tested Self-Calibrating 12-Bit
Plus Sign A D Converter with Sample-and-Hold
General Description
The ADC12441 is a CMOS 12-bit plus sign successive ap-
proximation analog-to-digital converter whose dynamic
specifications (S N THD etc ) are tested and guaranteed
On request the ADC12441 goes through a self-calibration
cycle that adjusts positive linearity and full-scale errors to
less than g LSB each and zero error to less than
g1 LSB The ADC12441 also has the ability to go through
an Auto-Zero cycle that corrects the zero error during every
conversion
The analog input to the ADC12441 is tracked and held by
the internal circuitry and therefore does not require an ex-
ternal sample-and-hold A unipolar analog input voltage
range (0V to a5V) or a bipolar range (b5V to a5V) can be
accommodated with g5V supplies
The 13-bit word on the outputs of the ADC12441 gives a 2’s
complement representation of negative numbers The digi-
tal inputs and outputs are compatible with TTL or CMOS
logic levels
Features
Y Self-calibration provides excellent temperature stability
Y Internal sample-and-hold
Y Bipolar input range with single a5V reference
Applications
Y Digital signal processing
Y Telecommunications
Y Audio
Y High resolution process control
Y Instrumentation
Key Specifications
Y Resolution
Y Conversion Time
Y Bipolar Signal Noise
Y Total Harmonic Distortion
Y Aperture Time
Y Aperture Jitter
Y Zero Error
Y Positive Full Scale Error
Y Power Consumption g5V
Y Sampling rate
12 bits plus sign
13 8 ms (max)
76 5 dB (min)
b75 dB (max)
100 ns
100 psrms
g1 LSB (max)
g1 LSB (max)
70 mW (max)
55 kHz (max)
TRI-STATE is a registered trademark of National Semiconductor Corporation
Simplified Block Diagram
Connection Diagram
Dual-In-Line Package
C1995 National Semiconductor Corporation TL H 11017
Top View
TL H 11017 – 2
Order Number
ADC12441CMJ ADC12441CMJ 883
or ADC12441CIJ
See NS Package Number J28A
TL H 11017 – 1
RRD-B30M115 Printed in U S A






ADC12441 Datasheet, Funktion
Electrical Characteristics (Continued)
TL H 11017 – 6
FIGURE 1b Simplified Error Curve vs Output Code without Auto-Cal or Auto-Zero Cycles
FIGURE 1c Simplified Error Curve vs Output Code after Auto-Cal Cycle
Typical Performance Characteristics
Zero Error vs VREF
Zero Error Change vs
Ambient Temperature
TL H 11017 – 7
TL H 11017 – 8
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ADC12441 pdf, datenblatt
3 0 Analog Considerations (Continued)
For absolute accuracy where the analog input varies be-
tween very specific voltage limits the reference pin can be
biased with a time and temperature stable voltage source
In general the magnitude of the reference voltage will re-
quire an initial adjustment to null out full-scale errors
3 2 INPUT CURRENT
Because the input network of the ADC12441 is made up of
a switch and a network of capacitors a charging current will
flow into or out of (depending on the input voltage polarity)
of the analog input pin (VIN) on the start of the analog input
sampling period (tA) The peak value of this current will de-
pend on the actual input voltage applied
3 3 NOISE
The leads to the analog input pin should be kept as short as
possible to minimize input noise coupling Both noise and
undesired digital clock coupling to this input can cause er-
rors Input filtering can be used to reduce the effects of
these noise sources
3 4 INPUT BYPASS CAPACITORS
An external capacitor can be used to filter out any noise due
to inductive pickup by a long input lead and will not degrade
the accuracy of the conversion result
3 5 INPUT SOURCE RESISTANCE
The analog input can be modeled as shown in Figure 3
External RS will lengthen the time period necessary for the
voltage on CREF to settle to within LSB of the analog
input voltage With fCLK e 2 MHz tA e 7 clock periods e
3 5 ms RS s 1 kX will allow a 5V analog input voltage to
settle properly
3 6 POWER SUPPLIES
Noise spikes on the VCC and Vb supply lines can cause
conversion errors as the comparator will respond to this
noise The A D is especially sensitive during the auto-zero
or auto-cal procedures to any power supply spikes Low in
ductance tantalum capacitors of 10 mF or greater paralleled
with 0 1 mF ceramic capacitors are recommended for supply
bypassing Separate bypass capacitors whould be placed
close to the DVCC AVCC and Vb pins If an unregulated
voltage source is available in the system a separate
LM340LAZ-5 0 voltage regulator for the A-to-D’s VCC (and
other analog circuitry) will greatly reduce digital noise on the
supply line
3 7 THE CALIBRATION CYCLE
On power up the ADC12441 goes through an Auto-Cal cy-
cle which cannot be interrupted Since the power supply
reference and clock will not be stable at power up this first
calibration cycle will not result in an accurate calibration of
the A D A new calibration cycle needs to be started after
the power supplies reference and clock have been given
enough time to stabilize During the calibration cycle cor-
rection values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full scale
offset and linearity errors down to the specified limits Full
scale error typically changes g0 1 LSB over temperature
and linearity error changes even less therefore it should be
necessary to go through the calibration cycle only once af-
ter power up if auto-zero is used to correct the zero error
change
3 8 THE AUTO-ZERO CYCLE
To correct for any change in the zero (offset) error of the
A D the auto-zero cycle can be used It may be necessary
to do an auto-zero cycle whenever the ambient temperature
changes significantly (See the curved titled ‘‘Zero Error
Change vs Ambient Temperature’’ in the Typical Perform-
ance Characteristics ) A change in the ambient temperature
will cause the VOS of the sampled data comparator to
change which may cause the zero error of the A D to be
greater than g1 LSB An auto-zero cycle will maintain the
zero error to g1 LSB or less
FIGURE 3 Analog Input Equivalent Circuit
TL H 11017 – 21
12

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