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ADC12281 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC12281
Beschreibung 12-Bit/ 20 MSPS Single-Ended Input/ Pipelined A/D Converter
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 16 Seiten
ADC12281 Datasheet, Funktion
March 2000
ADC12281
12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D
Converter
General Description
The ADC12281 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 20 megasamples per second (MSPS). It uti-
lizes a pipeline architecture to minimize die size and power
dissipation. Self-calibration and error correction maintain ac-
curacy and performance over temperature.
The ADC12281 operates on a 5V power supply and can digi-
tize single-ended analog input signals in the range of 0V to
2V. A single convert clock controls the conversion operation
and all digital I/O is TTL compatible.
The ADC12881 is designed to minimize external compo-
nents necessary for the analog input interface. An internal
sample-and-hold circuit samples the single-ended analog in-
put and an internal amplifier buffers the reference voltage in-
put.
The Power Down feature reduces power consumption to
20 mW, typical.
The ADC12281 is available in the 32-lead TQFP package
and is designed to operate over the industrial temperature
range of −40˚C to +85˚C.
Features
n Single 5V power supply
n Single-ended analog input
n Internal sample-and-hold
n Internal reference buffer amplifier
n Low offset and gain errors
Key Specifications
n Resolution
n Conversion rate
n DNL
n SNR
n ENOB
n Analog input range
n Supply voltage
n Power consumption, 20 MHz
Applications
n Digital signal processing front end
n Digital television
n Radar
n High speed data links
n Waveform digitizers
n Quadrature demodulation
12 bits
up to 20 MSPS
0.35 LSB (typ)
65.5 dB (typ)
10.5 bits (typ)
2 VPP (min)
+5V ±5%
443 mW (typ)
Connection Diagram
DS101027-1
32-Lead TQFP Package
Order Number ADC12281CIVT
See NS Package Number VBE32A
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101027
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ADC12281 Datasheet, Funktion
DC and Logic Electrical Characteristics (Continued)
The following specifications apply for AGND = DGND = DGND I/O = 0V, VA = VD = VD I/O = +5V, PD = +5V, VREF = +2.0V,
fCLK = 20 MHz, 3 VP-P at 50% duty cycle, CL = 25 pF/pin. After Auto-Cal. Boldface limits apply for TA = TJ = TMIN to TMAX;
all other limits TA = TJ = 25˚C (Notes 7, 8, 9).
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
VOH
VOL
IOZ
+ISC
Logical “1” Output Voltage
Logical “0” Output Voltage
TRI-STATE Output Current
Output Short Circuit Source
Current
IOUT = −1 mA
IOUT = 1.6 mA
VOUT = 3V or 5V
VOUT = 0V
VD I/O = 3V, VOUT = 0V
100
−100
−29
4 V (min)
0.4 V (max)
nA
nA
mA
−ISC
Output Short Circuit Sink Current
POWER SUPPLY CHARACTERISTICS
VD I/O = 3V, VOUT = VD
28
mA
IA Analog Supply Current
PD = DGND (active)
PD = VD I/O (power-down mode)
85
3.5
100 mA (max)
mA
ID Digital Supply Current
PD = DGND (active)
PD = VD I/O (power-down mode)
3.6
1
6 mA (max)
mA
Total Power Consumption
PD = DGND (active)
PD = VD I/O (power-down mode)
443
20
530 mW (max)
typ
AC Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, VA = VD = VD I/O = +5V, PD = +5V, VREF = +2.0V,
fCLK = 20 MHz, 3 VP-P at 50% duty cycle, CL = 25 pF/pin. After Auto-Cal. Boldface limits apply for TA = TJ = TMIN to TMAX;
all other limits TA = TJ = 25˚C (Notes 7, 8, 9).
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
fCLK Conversion Clock (CLOCK) Frequency
0.5 MHz (min)
20 MHz (max)
tCONV
Conversion Latency
10
Clock
Cycles
tOD
IOZ
tOE
tWCAL
tRDYC
tCAL
tWPD
tRDYPD
tPD
Data Output Delay after Rising CLK Edge
Data Outputs into TRI-STATE Mode
Data Outputs Active after TRI-STATE
Calibration Request Pulse Width
Ready Low after CAL Request
Calibration Cycle
Power-Down Pulse Width
Ready Low after PD Request
Power-Down Mode Exit Cycle
5
16
10
3
3
4000
3
3
4000
17 ns (max)
ns
ns
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test condi-
tions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = DGND I/O = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA, VD or VD I/O), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (TJMAX) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJMAX, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PD MAX = (TJMAX – TA) /θJA. In the 32-pin
TQFP, θJA is 79˚C/W, so PD MAX = 1,582 mW at 25˚C and 949 mW at the maximum operating ambient temperature of 75˚C. Note that the power dissipation of this
device under normal operation will typically be about 125 mW (typical power dissipation + 20 mW TTL output loading). The values for maximum power dissipation
listed above will be reached only when the ADC12281 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply volt-
ages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kresistor. Machine model is 220 pF discharged through 0.
Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
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ADC12281 pdf, datenblatt
Functional Description
The ADC12881 is a monolithic CMOS analog-to-analog con-
verter capable of converting single-ended analog input sig-
nals into 12-bit digital words at 20 megasamples per second
(MSPS). This device utilizes a proprietary pipeline architec-
ture and algorithm to minimize die size and power dissipa-
tion. The ADC12281 uses self-calibration and digital error
correction to maintain accuracy and performance over tem-
perature and a single-ended to differential conversion circuit
to ease input interfacing while achieving differential input
performance.
The ADC12281 has an input signal sample-and-hold ampli-
fier and internal reference buffer. The analog input and the
reference voltage are converted to differential signals for in-
ternal use. Using differential signals in the analog conversion
core reduces crosstalk and noise pickup from the digital sec-
tion and power supply.
The pipeline conversion core has 15 sequential signal pro-
cessing stages. Each stage receives an analog signal from
the previous stage (called “residue”) and produces a 1-bit
digital output that is sent to the digital correction module. At
each stage the analog signal received from the previous
stage is compared to an internally-generated reference level.
It is then amplified by a factor of 2, and, depending on the
output of the comparator, the internal reference signal may
be subtracted from the amplifier output. This produces the
residue that is passed to the next stage.
The calibration module is activated at power-on or by user
request. During calibration the conversion core is put into a
special mode of operation in order to determine inherent er-
rors in the analog conversion blocks such as op amp offsets,
comparator offsets, capacitor mismatches, etc. The calibra-
tion procedure determines coefficients for each digital output
bit from the conversion core and stores these coefficients in
on-chip RAM. The digital correction module uses the coeffi-
cients in RAM to convert the raw data bits from the conver-
sion core into the 12-bit digital output code.
Applications Information
1.0 ANALOG INPUTS. The analog inputs of the ADC12881
are the reference input (VREF) and the signal input (VIN).
1.1 Reference Input. The VREF input must be driven from an
accurate, stable reference voltage source between 1.8V and
2.2V and bypassed to a clean, low-noise ground with a
monolithic ceramic capacitor (nominally 0.01 µF).
1.2 Analog Signal Input. This analog input is a switch fol-
lowed by an integrator. The input capacitance changes with
the clock level, appearing as 10 pF when the clock is low,
and 15 pF when the clock is high. Since a dynamic capaci-
tance is more difficult to drive than is a fixed capacitance,
choose an amplifier that can drive this type of load. The
CLC409 has been found to be a good device to drive the
ADC12281. Do not drive the input beyond the supply rails.
The VIN input must be driven with a low impedance signal
source that does not add any distortion to the input signal.
The ground reference for the VIN input is the VIN COM pin.
The VIN COM pin should be connected to a clean point in the
analog ground plane. The ground return for the reference
voltage should enter the ground plane at the same point as
does the VIN COM pin.
To simplify the interface, the ADC12281 has an internal
single-ended to differential buffer. This permits performance
you would expect to see with a differential input while driving
the input with a single-ended signal.
To achieve maximum performance, you should be careful to
maintain short input and ground runs in lines carrying signal
current. The signal ground line, VIN COM and the reference
ground should all enter the analog ground plane at the same
point, as indicated in Figure 5.
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