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PDF ADC12181EVAL Data sheet ( Hoja de datos )
| Número de pieza | ADC12181EVAL | |
| Descripción | 12-Bit/ 5 MHz Self-Calibrating/ Pipelined A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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March 2000
ADC12081
12-Bit, 5 MHz Self-Calibrating, Pipelined A/D Converter
with Internal Sample & Hold
General Description
The ADC12081 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 5 megasamples per second (MSPS). The
ADC12081 utilizes an innovative pipeline architecture to
minimize die size and power consumption. The ADC12081
uses self-calibration and error correction to maintain accu-
racy and performance over temperature.
The ADC12081 converter operates on a 5V power supply
and can digitize analog input signals in the range of 0 to 2V.
A single convert clock controls the conversion operation. All
digital I/O is TTL compatible.
The ADC12081 is designed to minimize external compo-
nents necessary for the analog input interface. An internal
sample-and-hold circuit samples the analog input and an in-
ternal amplifier buffers the reference voltage input.
The ADC12081 is available in the 32-lead TQFP package
and is designed to operate over the extended commercial
temperature range of -40˚C to +85˚C.
Features
n Single 5V power supply
n Simple analog input interface
n Internal Sample-and-hold
n Internal Reference buffer amplifier
n Low power consumption
Key Specifications
n Resolution
n Conversion Rate
n DNL
n SNR
n ENOB
n Analog Input Range
n Supply Voltage
n Power Consumption, 5 MHz
Applications
n Image processing front end
n PC-based data acquisition
n Scanners
n Fax machines
n Waveform digitizer
12 Bits
5 Msps (min)
±0.35 LSB (typ)
68 dB (typ)
10.9 Bits (typ)
2 Vpp (min)
+5V ±5%
105 mW (typ)
Connection Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation. CN
© 2000 National Semiconductor Corporation DS100150
DS100150-1
www.national.com
1 page  
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Voltage on Any Output
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation
ESD Susceptibility
Human Body Model
Machine Model
Soldering Temp., Infrared, 10
sec.(Note 6)
6.5V
−0.3V to V+ +0.3V
±25mA
±50mA
See (Note 4)
1500V
150V
300˚C
Storage Temp.
Maximum Junction Temp.
Operating Ratings
Operating Temp. Range
Supply Voltage
VD I/O
VREF Input
CLOCK, CAL, PD, OE
|AGND −DGND|
−65˚C to +150˚C
150˚C
−40˚C ≤ TA ≤ +85˚C
+4.75V to +5.25V
+2.7V to VD
1.8V to 2.2V
−0.05V to VD + 0.05V
≤100mV
Converter Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, VA = VD = VD I/O = +5V, PD = +5V, VREF = +2.0V,
fCLK = 5MHz, CL = 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for TA = TJ to TMIN to TMAX: all other
limits TA = TJ = 25˚C (Notes 7, 8) and (Note 9)
Symbol
Parameter
Conditions
Typical
(Note
10)
Limits
(Note
11)
Units
(Limits)
Static Converter Characteristics
Resolution with No Missing Codes
12 Bits(min)
INL Integral Non Linearity
±0.6
±1.7
LSB( max)
DNL
Differential Non Linearity
±0.35
±0.75
LSB( max)
Full-Scale Error
±0.05
±0.1
%FS(max)
Zero Error
±0.15
±0.24
%FS(max)
Dynamic Converter Characteristics
BW Full Power Bandwidth
100 MHz
SNR
Signal-to-Noise Ratio
SINAD Signal-to-Noise & Distortion
ENOB Effective Number of Bits
THD
Total Hamonic Distortion
SFDR Spurious Free Dynamic Range
Reference and Analog Input Characteristics
fin = 2.5 MHz, VIN = 2.0VP-P
fin = 2.5 MHz, VIN = 2.0VP-P
fin = 2.5 MHz, VIN = 2.0VP-P
fin = 2.5 MHz, VIN = 2.0VP-P
fin = 2.5 MHz, VIN = 2.0VP-P
68 65
67.6 64.5
10.9 10.4
79
79
dB
dB
Bits
dB
dB
VIN Input Voltage Range
CIN VIN Input Capacitance
VREF = 2.0V
VIN = 1.0Vdc +
0.7Vrms
(CLK
LOW)
(CLK
HIGH)
0
VREF
V(min)
V(max)
10 pF
15 pF
VREF
Reference Voltage (Note 14)
1.8 V(min)
2.00
2.2 V(max)
Reference Input Leakage Current
10 µA
Reference Input Resistance
1 MΩ(min)
5 www.national.com
5 Page 
Timing Diagrams (Continued)
DS100150-22
FIGURE 4. Reset and Calibration Timing
Functional Description
Applications Information
The ADC12081 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 5 megasamples per second (MSPS). This
device utilizes a proprietary pipeline architecture and algo-
rithm to minimize die size and power consumption. The
ADC12081 uses self-calibration and digital error correction
to maintain accuracy and performance over temperature.
The ADC12081 has an input sample-and-hold amplifier and
internal reference buffer. The analog input and the reference
voltage are converted to differential signals for internal use.
Using differential signals in the analog conversion core re-
duces crosstalk and noise pickup from the digital section and
power supply.
1.0 Analog Inputs.
The ADC12081 has two single-ended analog inputs. VREF is
the reference input and VIN is the signal input.
1.1 Reference Input The VREF input must be driven from an
accurate, stable reference voltage source. of 1.8V to 2.2V,
and bypassed to a clean, quiet point in analog ground.
1.2 Analog Signal Input The VIN input must be driven with
a low impedance signal source that does not add any distor-
tion to the input signal. The ground reference for the VIN in-
put is the VINCOM pin. The VINCOM pin must be connected to
a clean, quiet point in analog ground.
The pipeline conversion core has 15 sequential signal pro-
cessing stages. Each stage receives an analog signal from
the previous stage (called “residue” ) and produces a 1-bit
digital output that is sent to the digital correction module. At
each stage the analog signal received from the previous
stage is compared to an internally generated reference level.
It is then amplified by a factor of 2, and, depending on the
output of the comparator, the internal reference signal may
be subtracted from the amplifier output. This produces the
residue that is passed to the next stage.
The calibration module is activated at power-on or by user
request. During calibration the conversion core is put into a
special mode of operation in order to determine inherent er-
rors in the analog conversion blocks and to determine cor-
rection coefficients for each digital output bit from the con-
version core and stores these coefficients in RAM. The
digital correction module uses the coefficients in RAM to
convert the raw data bits from the conversion core into the
12-bit digital output code.
2.0 Digital Inputs
The ADC12081 has four digital inputs. They are CLOCK,
CAL, OE and PD.
2.1 CLOCK The CLOCK signal drives an internal phase de-
lay loop to create timing for the ADC. The clock input should
be driven with a stable, low phase jitter TTL level clock signal
in the range of 0.5 to 5 MHz. The trace carrying the clock sig-
nal should be as short as possible. This trace should not
cross any other signal line, analog or digital, not even at 90˚.
A 100 Ohm resistor should be placed in series with the
CLOCK pin, as close to the pin as possible.
2.2 CAL The level sensitive CAL input must be pulsed high
for at least three clock cycles to begin ADC calibration. For
best performance, calibration should be performed about ten
seconds after power up, after resetting the ADC, and after
the temperature has changed by more than 50˚C since the
last calibration was performed.
Calibration should be performed at the same clock fre-
quency that the ADC12081 will be used for conversions to
minimize offset errors. Calibration takes 4000 clock cycles.
Irrelevant data may appear during CAL.
11 www.national.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADC12181EVAL.PDF ] | |
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