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ADC12181CIVT Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC12181CIVT
Beschreibung 12-Bit/ 10 MHz Self-Calibrating/ Pipelined A/D Converter with Internal Sample & Hold
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 17 Seiten
ADC12181CIVT Datasheet, Funktion
November 2002
ADC12181
12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter
with Internal Sample & Hold
General Description
The ADC12181 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 10 megasamples per second (MSPS). The
ADC12181 utilizes an innovative pipeline architecture to
minimize die size and power consumption. Self-calibration
and error correction maintain accuracy and performance
over temperature.
The ADC12181 converter operates on a 5V power supply
and can digitize analog input signals in the range of 0 to 2V.
A single convert clock controls the conversion operation. All
digital I/O is TTL compatible.
The ADC12181 is designed to minimize external compo-
nents necessary for the analog input interface. An internal
sample-and-hold circuit samples the analog input and an
internal amplifier buffers the reference voltage input.
The ADC12181 is available in the 32-lead TQFP package
and is designed to operate over the extended commercial
temperature range of -40˚C to +85˚C.
Features
n Single 5V power supply
n Simple analog input interface
n Internal Sample-and-hold
n Internal Reference buffer amplifier
n Low power consumption
Key Specifications
n Resolution
n Conversion Rate
n DNL
n SNR
n ENOB
n Analog Input Range
n Supply Voltage
n Power Consumption, 10 MHz
Applications
n Image processing front end
n PC-based data acquisition
n Scanners
n Fax machines
n Waveform digitizer
12 Bits
10 Msps (min)
±0.4 LSB (typ)
65 dB (typ)
10.4 Bits (typ)
2 Vpp (min)
+5V ±5%
235 mW (typ)
Connection Diagram
Ordering Information
Industrial
(−40˚C TA +85˚C)
ADC12181CIVT
© 2002 National Semiconductor Corporation DS101039
10103901
Package
32 pin TQFP
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ADC12181CIVT Datasheet, Funktion
DC and Logic Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, VA = VD = VD I/O = +5V, PD = +5V, VREF = +2.0V,
fCLK = 10MHz, CL = 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for TA = TMIN to TMAX; all other limits
TA = TJ = 25˚C (Note 7) (Note 8) and (Note 9)
Symbol
Parameter
Conditions
Typical
(Note
10)
Limits
(Note
11)
Units
(Limits)
CLK, OE Digital Input Characteristics
VIH Logical "1" Input Voltage
VIL Logical "0" Input Voltage
IIH Logical "1" Input Current
IIL Logical "0" Input Current
CIN VIN Input Capacitance
D0 - D11 Digital Output Characteristics
V+ = 5.25V
V+ = 4.75V
VIN = 5.0V
VIN = 0V
2.0 V(min)
0.8 V(min)
5 µA
−5 µA
8 pF
VOH
VOL
IOZ
+ISC
Logical "1" Output Voltage
Logical "0" Output Voltage
TRI-STATE Output Current
Output Short Circuit Source
Current
IOUT = −1mA
IOUT = 1.6mA
VOUT = 3V or 5V
VOUT = 0V
VDDO= 3V, VOUT = 0V
4 V (min)
0.4 V (max)
10 µA
−10 µA
mA(min)
−14
−ISC
Output Short Circuit Sink Current
Power Supply Characteristics
VDDO= 3V, VOUT = VO
16 mA(min)
IA Analog Supply Current
PD = VD I/O
PD = DGND
2.5 4 mA(max)
45 55 mA(max)
ID Digital Supply Current
PD = VD I/O
PD = DGND
0.5 2 mA(max)
2 3 mA(max)
Total Power Consumption
PD = VD I/O
PD = DGND
15 30 mW(max)
235 290 mW(max)
AC Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, VA = VD = VD I/O = +5V, PD = +5V, VREF = +2.0V,
fCLK = 10 MHz, CL = 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for TA = TMIN to TMAX; all other limits
TA = TJ = 25˚C (Note 7) (Note 8) and (Note 10)
Symbol
Parameter
Conditions
Typical
(Note
10)
Limits
(Note
11)
Units
(Limits)
fCLK Clock Frequency
1 MHz(min)
10 MHz(max)
Clock Duty Cycle
50 %
tCONV
Conversion Latency
10.25
Clock
Cycles
tOD
tDIS
tEN
tWCAL
tRDYC
tCAL
tWPD
tRDYPD
tPD
Data output delay after rising clk
edge
Data outputs into Tristate mode
Data outputs active after Tristate
Calibration request pulse width
Ready Low after CAL request
Calibration cycle
Power-down pulse width
Ready Low after PD request
Power down mode exit cycle
VD I/O = 3V
VD I/O = 5V
44
ns
40
21 nA (max)
21 ns (max)
3 Tclk(min)
3 Tclk
4000
Tclk
3 Tclk(min)
3 Tclk
4000
Tclk
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ADC12181CIVT pdf, datenblatt
Timing Diagrams (Continued)
FIGURE 4. Reset and Calibration Timing
10103922
Functional Description
The ADC12181 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 10 megasamples per second (MSPS). This
device utilizes a proprietary pipeline architecture and algo-
rithm to minimize die size and power consumption. The
ADC12181 uses self-calibration and digital error correction
to maintain accuracy and performance over temperature.
The ADC12181 has an input sample-and-hold amplifier and
internal reference buffer. The analog input and the reference
voltage are converted to differential signals for internal use.
Using differential signals in the analog conversion core re-
duces crosstalk and noise pickup from the digital section and
power supply.
The pipeline conversion core has 15 sequential signal pro-
cessing stages. Each stage receives an analog signal from
the previous stage (called “residue” ) and produces a 1-bit
digital output that is sent to the digital correction module. At
each stage the analog signal received from the previous
stage is compared to an internally generated reference level.
It is then amplified by a factor of 2, and, depending on the
output of the comparator, the internal reference signal may
be subtracted from the amplifier output. This produces the
residue that is passed to the next stage.
The calibration module is activated at power-on or by user
request. During calibration the conversion core is put into a
special mode of operation in order to determine inherent
errors in the analog conversion blocks and to determine
correction coefficients for each digital output bit from the
conversion core and stores these coefficients in RAM. The
digital correction module uses the coefficients in RAM to
convert the raw data bits from the conversion core into the
12-bit digital output code.
Applications Information
1.0 ANALOG INPUTS
The ADC12181 has two single-ended analog inputs. VREF is
the reference input and VIN is the signal input.
1.1 Reference Input
The VREF input must be driven from an accurate, stable
reference voltage source. of 1.8V to 2.2V, and bypassed to a
clean, quiet point in analog ground.
1.2 Analog Signal Input
The VIN input must be driven with a low impedance signal
source that does not add any distortion to the input signal.
The ground reference for the VIN input is the VINCOM pin. The
VINCOM pin must be connected to a clean, quiet point in
analog ground.
2.0 DIGITAL INPUTS
The ADC12181 has four digital inputs. They are CLOCK,
CAL, OE and PD.
2.1 CLOCK
The CLOCK signal drives an internal phase delay loop to
create timing for the ADC. The clock input should be driven
with a stable, low phase jitter TTL level clock signal in the
range of 1 to 10 MHz. The trace carrying the clock signal
should be as short as possible. This trace should not cross
any other signal line, analog or digital, not even at 90˚. A 100
Ohm resistor should be placed in series with the CLOCK pin,
as close to the pin as possible.
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