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PDF ADC12130 Data sheet ( Hoja de datos )
| Número de pieza | ADC12130 | |
| Descripción | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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March 2000
ADC12130/ADC12132/ADC12138
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D
Converters with MUX and Sample/Hold
General Description
The ADC12130, ADC12132 and ADC12138 are 12-bit plus
sign successive approximation A/D converters with serial I/O
and configurable input multiplexer. The ADC12132 and
ADC12138 have a 2 and an 8 channel multiplexer, respec-
tively. The differential multiplexer outputs and A/D inputs are
available on the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2
pins. The ADC12130 has a two channel multiplexer with the
multiplexer outputs and A/D inputs internally connected. The
ADC12130 family is tested with a 5 MHz clock. On request,
these A/Ds go through a self calibration process that adjusts
linearity, zero and full-scale errors to typically less than ±1
LSB each.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or
pseudo-differential modes. A fully differential unipolar analog
input range (0V to +5V) can be accommodated with a single
+5V supply. In the differential modes, valid outputs are ob-
tained even when the negative inputs are greater than the
positive because of the 12-bit plus sign output data format.
The serial I/O is configured to comply with the NSC MI-
CROWIRE™. For voltage references, see the LM4040 or
LM4041.
Features
n Serial I/O (MICROWIRE, SPI and QSPI Compatible)
n 2 or 8 channel differential or single-ended multiplexer
n Analog input sample/hold function
n Power down mode
n Programmable acquisition time
n Variable digital output word length and format
n No zero or full scale adjustment required
n 0V to 5V analog input range with single 5V power
supply
Key Specifications
n Resolution: 12-bit plus sign
n 12-bit plus sign conversion time: 8.8 µs (max)
n 12-bit plus sign throughput time: 14 µs (max)
n Integral linearity error: ±2 LSB (max)
n Single supply: 3.3V or 5V ±10%
n Power consumption
— 3.3V
15 mW (max)
— 3.3V power down
40 µW (typ)
— 5V
33 mW (max)
— 5V power down
100 µW (typ)
Applications
n Pen-based computers
n Digitizers
n Global positioning systems
ADC12138 Simplified Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
COPS™ microcontrollers, HPC™ and MICROWIRE™ are trademarks of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS012079
DS012079-1
www.national.com
1 page  
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage
(V+ = VA+ = VD+)
Voltage at Inputs and Outputs
except CH0–CH7 and COM
Voltage at Analog Inputs
CH0–CH7 and COM
|VA+ − VD+|
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at
TA = 25˚C (Note 4)
ESD Susceptability (Note 5)
Human Body Model
Soldering Information
N Packages (10 seconds)
SO Package (Note 6):
Vapor Phase (60 seconds)
Infrared (15 seconds)
6.5V
−0.3V to V+ +0.3V
GND −5V to V+ +5V
300 mV
±30 mA
±120 mA
500 mW
1500V
260˚C
215˚C
220˚C
Storage Temperature
−65˚C to +150˚C
Operating Ratings (Notes 1, 2)
Operating Temperature Range
ADC12130CIN, ADC12130CIWM,
ADC12132CIMSA,
ADC12138CIMSA,
ADC12138CIN, ADC12138CIWM
Supply Voltage (V+ = VA+ = VD+)
|VA+ − VD+|
VREF+
VREF−
VREF (VREF+ − VREF−)
VREF Common Mode Voltage Range
TMIN ≤ TA ≤ TMAX
−40˚C ≤ TA ≤ +85˚C
+3.0V to +5.5V
≤ 100 mV
0V to VA+
0V to VREF+
1V to VA+
A/DIN1, A/DIN2, MUXOUT1
and MUXOUT2 Voltage Range
A/D IN Common Mode Voltage
Range
0.1 VA+ to 0.6 VA+
0V to VA+
0V to VA+
Converter Electrical Characteristics
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2.048V
VREF+ ≤
25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN
to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution
12 + sign Bits (min)
+ILE
Positive Integral Linearity Error After Auto-Cal (Notes 12, 18)
±1/2
±2 LSB (max)
−ILE
Negative Integral Linearity Error After Auto-Cal (Notes 12, 18)
±1/2
±2 LSB (max)
DNL
Differential Non-Linearity
After Auto-Cal
±1.5
LSB (max)
Positive Full-Scale Error
After Auto-Cal (Notes 12, 18)
±1/2
±3.0
LSB (max)
Negative Full-Scale Error
After Auto-Cal (Notes 12, 18)
±1/2
±3.0
LSB (max)
Offset Error
After Auto-Cal (Notes 5, 18)
±1/2
±2 LSB (max)
DC Common Mode Error
VIN(+) = VIN(−) = 2.048V
After Auto-Cal (Note 15)
±2
LSB (max)
TUE
Total Unadjusted Error
After Auto-Cal
±1 LSB
(Notes 12, 13, 14)
5 www.national.com
5 Page 
AC Electrical Characteristics (Continued)
Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND
will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55
VDC to ensure accurate conversions.
DS012079-4
Note 8: To guarantee accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V+
pin.
Note 9: With the test condition for VREF (VREF+ − VREF−) given as +4.096V, the 12-bit LSB is 1.0 mV. For VREF = 2.5V, the 12-bit LSB is 610 µV.
Note 10: Typicals are at TJ = TA = 25˚C and represent most likely parametric norm.
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figure 2 and Figure 3).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions be-
tween −1 to 0 and 0 to +1 (see Figure 4).
Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTL logic levels, VOL = 0.4V for a falling edge and VOL = 2.4V for a rising edge. TRI-STATE output voltage is forced
to 1.4V.
Note 18: The ADC12130 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will re-
sult in a maximum repeatability uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then tA is 6, 10, 18 or 34 clock periods minimum and maximum.
Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
FIGURE 1. Transfer Characteristic
11
DS012079-5
www.national.com
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADC12130.PDF ] | |
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