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ADC12081CIVT Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC12081CIVT
Beschreibung 12-Bit/ 5 MHz Self-Calibrating/ Pipelined A/D Converter
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 16 Seiten
ADC12081CIVT Datasheet, Funktion
March 2000
ADC12081
12-Bit, 5 MHz Self-Calibrating, Pipelined A/D Converter
with Internal Sample & Hold
General Description
The ADC12081 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 5 megasamples per second (MSPS). The
ADC12081 utilizes an innovative pipeline architecture to
minimize die size and power consumption. The ADC12081
uses self-calibration and error correction to maintain accu-
racy and performance over temperature.
The ADC12081 converter operates on a 5V power supply
and can digitize analog input signals in the range of 0 to 2V.
A single convert clock controls the conversion operation. All
digital I/O is TTL compatible.
The ADC12081 is designed to minimize external compo-
nents necessary for the analog input interface. An internal
sample-and-hold circuit samples the analog input and an in-
ternal amplifier buffers the reference voltage input.
The ADC12081 is available in the 32-lead TQFP package
and is designed to operate over the extended commercial
temperature range of -40˚C to +85˚C.
Features
n Single 5V power supply
n Simple analog input interface
n Internal Sample-and-hold
n Internal Reference buffer amplifier
n Low power consumption
Key Specifications
n Resolution
n Conversion Rate
n DNL
n SNR
n ENOB
n Analog Input Range
n Supply Voltage
n Power Consumption, 5 MHz
Applications
n Image processing front end
n PC-based data acquisition
n Scanners
n Fax machines
n Waveform digitizer
12 Bits
5 Msps (min)
±0.35 LSB (typ)
68 dB (typ)
10.9 Bits (typ)
2 Vpp (min)
+5V ±5%
105 mW (typ)
Connection Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation. CN
© 2000 National Semiconductor Corporation DS100150
DS100150-1
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ADC12081CIVT Datasheet, Funktion
DC and Logic Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, VA = VD = VD I/O = +5V, PD = +5V, VREF = +2.0V,
fCLK = 50MHz, CL = 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for TA = TMIN to TMAX; all other limits
TA = TJ = 25˚C (Note 7) (Note 8) and (Note 9)
Symbol
Parameter
Conditions
Typical
(Note
10)
Limits
(Note
11)
Units
(Limits)
CLK, OE Digital Input Characteristics
VIH Logical 1Input Voltage
VIL Logical 0Input Voltage
IIH Logical 1Input Current
IIL Logical 0Input Current
CIN VIN Input Capacitance
D0 - D11 Digital Output Characteristics
V+ = 5.25V
V+ = 4.75V
VIN = 5.0V
VIN = 0V
2.0 V(min)
0.8 V(min)
5 µA
−5 µA
8 pF
VOH
VOL
IOZ
+ISC
Logical 1Output Voltage
Logical 0Output Voltage
TRI-STATE®Output Current
Output Short Circuit Source
Current
IOUT = −1mA
IOUT = 1.6mA
VOUT = 3V or 5V
VOUT = 0V
VDDO= 3V, VOUT = 0V
4 V (min)
0.4 V (max)
10 µA
−10 µA
mA(min)
−14
−ISC
Output Short Circuit Sink Current
VDDO= 3V, VOUT = VO
16
mA(min)
Power Supply Characteristics
IA Analog Supply Current
PD = VDDO
PD = DGND
2.5 4 mA(max)
20 26 mA(max)
ID Digital Supply Current
PD = VDDO
PD = DGND
0.5 2 mA(max)
1 2 mA(max)
Total Power Consumption
PD = VDDO
PD = DGND
15 30 mW(max)
105 140 mW(max)
AC Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, VA = VD = VD I/O = +5V, PD = +5V, VREF = +2.0V,
fCLK = 5 MHz, CL = 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for TA = TMIN to TMAX; all other limits
TA = TJ = 25˚C (Note 7) (Note 8) and (Note 10)
Symbol
Parameter
Conditions
Typical
(Note
10)
Limits
(Note
11)
Units
(Limits)
fCLK Clock Frequency
0.5 MHz(min)
5 MHz(max)
Clock Duty Cycle
50 %
tCONV
Conversion Latency
10.25
Clock
Cycles
tOD Data output delay after rising clk
edge
40 ns
tDIS
tEN
tWCAL
tRDYC
tCAL
tWPD
tRDYPD
tPD
Data outputs into Tristate mode
Data outputs active after Tristate
Calibration request pulse width
Ready Low after CAL request
Calibration cycle
Power-down pulse width
Ready Low after PD request
Power down mode exit cycle
21 nA (max)
21 ns (max)
3 Tclk(min)
3 Tclk
4000
Tclk
3 Tclk(min)
3 Tclk
4000
Tclk
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
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ADC12081CIVT pdf, datenblatt
Applications Information (Continued)
2.3 OE Pin The OE pin is used to control the state of the out-
puts. When the OE pin is low, the output buffers go into the
active state. When the OE input is high, the output buffers
are in the high impedance state.
2.4 PD Pin The PD pin, when high, holds the ADC12081 in
a power-down mode where power consumption is typically
less than 15 mW to conserve power when the converter is
not being used. The ADC12081 will begin normal operation
within tPD after this pin is brought low, provided a valid
CLOCK input is present. The data in the pipeline is corrupted
while in the power down mode. The ADC12081 should be re-
calibrated after a power-down cycle to ensure optimum per-
formance.
3.0 Outputs
The ADC12081 has three analog outputs: reference output
voltages VRN, VRM , and VRP. There are 14 digital outputs:
12 Data Output pins, Ready and OR (Out of range).
3.1 Reference Output Voltages The reference output volt-
ages are made available only for the purpose of bypassing
with capacitors to a clean analog ground. The recommended
bypass capacitors are 0.1µF ceramic chip capacitors. Do not
load these pins.
3.2 Ready Output The Ready output goes high to indicate
that the converter is ready for operation. This signal will go
low when the converter is Calibration or Power Down made.
3.3 OR (Out of Range) Output The OR output goes high
when the analog input is below GND or above VREF. This
output is low when the input signal is in the valid range of op-
eration (0V VIN VREF).
3.4 Data Outputs The Data Outputs are TTL/CMOS com-
patible. The output data format is 12 bits straight binary.
Minimizing the digital output currents will help to minimize
noise due to output switching. This can be done by connect-
ing buffers between the ADC outputs and any other circuitry.
Only one buffer input should be connected to each output.
Additionally, inserting series resistors of 47 to 56 Ohms right
at the digital outputs, close to the ADC pins, will isolate the
outputs from other circuitry and limit output currents.
4.0 Power Supply Considerations
Each power pin should be bypassed with a parallel combina-
tion of a 10µF capacitor and a 0.1µF ceramic chip capacitor.
The chip capacitors should be within 1/2 centimeter of the
power pins. Leadless chip capacitors are preferred because
they provide low lead inductance.
The converter’s digital logic supply (VD) should be well iso-
lated from the supply that is used for other digital circuitry on
the board. A common power supply should be used for both
VA (analog supply) and VD (digital supply), and each of these
supply pins should be separately bypassed with a 0.1µF ce-
ramic capacitor and a low ESR 10µF electrolytic capacitor. A
ferrite bead or inductor should be used between VA and VD
to prevent noise coupling from the digital supply into the ana-
log circuit.
VD I/O is the power pin for the output driver. This pin may be
supplied with a potential between 3V and 5V. This makes it
easy to interface the ADC12081 with 3V or 5V logic families.
Powering the VD I/O from 3 Volts will also reduce power con-
sumption and noise generation due to output switching. DO
NOT operate the VD I/O at a voltage higher than VD or VA!
All power supplies connected to the device should be ap-
plied simultaneously.
As is the case with all high speed converters, the ADC12081
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be minimized, keeping it below
100mV P-P.
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