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ADC1205CCJ-1 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC1205CCJ-1
Beschreibung 12-Bit Plus Sign mP Compatible A/D Converters
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 18 Seiten
ADC1205CCJ-1 Datasheet, Funktion
June 1994
ADC1205 ADC1225 12-Bit Plus Sign
mP Compatible A D Converters
General Description
The ADC1205 and ADC1225 are CMOS 12-bit plus sign
successive approximation A D converters The 24-pin
ADC1205 outputs the 13-bit data result in two 8-bit bytes
formatted high-byte first with sign extended The 28-pin
ADC1225 outputs a 13-bit word in parallel for direct inter-
face to a 16-bit data bus
Negative numbers are represented in 2’s complement data
format All digital signals are fully TTL and MOS compatible
A unipolar input (0V to 5V) can be accommodated with a
single 5V supply while a bipolar input (b5V to a5V) re-
quires the addition of a 5V negative supply
The ADC1205C and ADC1225C have a maximum non-lin-
earity of 0 0224% of Full Scale
Key Specifications
Y Resolution 12 bits plus sign
Y Linearity Error g1 LSB
Y Conversion Time 100 ms
Features
Y Compatible with all mPs
Y True differential analog voltage inputs
Y 0V to 5V analog voltage range with single 5V supply
Y TTL MOS input output compatible
Y Low power 25 mW max
Y Standard 24-pin or 28-pin DIP
Connection and Functional Diagrams
Dual-In-Line Package
Top View
Dual-In-Line Package
TL H 5676–1
Top View
TL H 5676–2
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 5676
See Ordering Information
TL H 5676 – 3
RRD-B30M115 Printed in U S A






ADC1205CCJ-1 Datasheet, Funktion
TL H 5676 – 22
FIGURE 1b Simplified Error Curve vs Output Code Without Zero and Fullscale Adjustment
FIGURE 1c Simplified Error Curve vs Output Code after Zero Fullscale Adjustment
TL H 5676 – 23
FIGURE 2 TRI-STATE Test Circuits and Waveforms
6
TL H 5676 – 7

6 Page









ADC1205CCJ-1 pdf, datenblatt
Functional Description (Continued)
TL H 5676 – 28
FIGURE 13
TL H 5676 – 29
When using this method of conversion only one strobe is
necessary and the rising edge of WR RD can be used to
read the current conversion results These methods reduce
the throughput time of the conversion since the RD and WR
cycles are combined
2 With the standard timing WR pulse width longer than the
conversion time a conversion is completed but the INTR will
never go low to signal the end of a conversion The output
latches will be updated and valid information will be avail-
able when the RD cycle is accomplished
3 Tying CS and RD low continuously and strobing WR to
initiate a conversion will also yield valid data The INTR will
never go low to signal the end of a conversion and the
digital outputs will always be enabled so using INTR to
strobe the WR line for a continuous conversion cannot be
done with this part
A simple stand-alone circuit can be accomplished by driving
WR with the inverse of the READY OUT signal using a sim-
ple inverter as shown below
FIGURE 14
12
TL H 5676 – 30

12 Page





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