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ADC1175CIJMX Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC1175CIJMX
Beschreibung 8-Bit/ 20MHz/ 60mW A/D Converter
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 17 Seiten
ADC1175CIJMX Datasheet, Funktion
January 2000
ADC1175
8-Bit, 20MHz, 60mW A/D Converter
General Description
The ADC1175 is a low power, 20 Msps analog-to-digital con-
verter that digitizes signals to 8 bits while consuming just 60
mW of power (typ). The ADC1175 uses a unique architecture
that achieves 7.5 Effective Bits. Output formatting is straight
binary coding.
The excellent DC and AC characteristics of this device, to-
gether with its low power consumption and +5V single supply
operation, make it ideally suited for many video, imaging and
communications applications, including use in portable
equipment. Furthermore, the ADC1175 is resistant to latchup
and the outputs are short-circuit proof. The top and bottom of
the ADC1175’s reference ladder is available for connections,
enabling a wide range of input possibilities.
The ADC1175 is offered in SOIC (EIAJ) and TSSOP. It is de-
signed to operate over the commercial temperature range of
-20˚C to +75˚C.
Features
n Internal Sample-and-Hold Function
n Single +5V Operation
n Internal Reference Bias Resistors
n Industry Standard Pinout
n TRI-STATE® Outputs
Key Specifications
n Resolution
8 Bits
n Maximum Sampling Frequency
20 Msps (min)
n THD
−55 dB (typ)
n DNL
0.75 LSB (max)
n ENOB
7.5 Bits (typ)
n Guaranteed No Missing Codes
n Differential Phase
0.5 Degree (typ)
n Differential Gain
0.7% (typ)
n Power Consumption
60mW (typ)
(excluding reference current)
Applications
n Video Digitization
n Digital Still Cameras
n Set Top Boxes
n Communications
n Medical Imaging
n Personal Computer Video Cameras
n Digital Television
n CCD Imaging
n Electro-Optics
Ordering Information
ADC1175CIJM
ADC1175CIJMX
ADC1175CIMTC
ADC1175CIMTCX
SOIC (EIAJ)
SOIC (EIAJ) (tape & reel)
TSSOP
TSSOP (tape & reel)
Pin Configuration
ADC1175 Pin Configuration
TRI-STATE® is a registered trademark of National Semiconductor Corporation. CN
© 2000 National Semiconductor Corporation DS100092
DS100092-1
www.national.com






ADC1175CIJMX Datasheet, Funktion
Converter Electrical Characteristics (Continued)
The
fCLK
following specifications apply
= 20MHz at 50% duty cycle.
for AVDD
Boldface
= DVDD = +5.0VDC,
limits apply for TA
OE = 0V,
= TMIN to
VRT =
TMAX;
+a2ll.o6tVh,eVr RlimB i=ts0T.6AV=,
CL =
25˚C
20 pF,
(Notes
7,
8)
Symbol
Parameter
Conditions
Typical Limits
(Note 9) (Note 9)
Units
AC Electrical Characteristics
SNR
Signal-to- Noise Ratio
fIN = 1.31 MHz, VIN = FS - 2 LSB
fIN = 4.43 MHz, VIN = FS - 2 LSB
fIN = 9.9 MHz, VIN = FS - 2 LSB
fIN = 4.43 MHz, fCLK = 30 MHz
47
47 44
42 dB(min)
45
SFDR
Spurious Free Dynamic
Range
fIN = 1.31 MHz, VIN = FS - 2 LSB
fIN = 4.43 MHz, VIN = FS - 2 LSB
fIN = 9.9 MHz, VIN = FS - 2 LSB
fIN = 4.43 MHz,fCLK = 30 MHz
56
58
53
46
dB
THD
Total Harmonic Distortion
fIN = 1.31 MHz, VIN = FS - 2 LSB
fIN = 4.43 MHz, VIN = FS - 2 LSB
fIN = 9.9 MHz, VIN = FS - 2 LSB
fIN = 4.43 MHz, fCLK = 30 MHz
−55
−57
−52
−47
dB
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = AVSS = DVSS = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AVSS or DVSS, or greater than AVDD or DVDD), the current at that pin should
be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.
Note 4: The absolute maximum junction temperatures (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance θJA, and the ambient temperature, TA, and can be calculated using the formula PDMAX = (TJmax - TA )/θJA. In the 24-pin
TSSOP, θJA is 92˚C/W, so PDMAX = 1,358 mW at 25˚C and 815 mW at the maximum operating ambient temperature of 75˚C. (Typical thermal resistance, θJA, of
this part is 98˚C/W for the EIAJ SOIC). Note that the power dissipation of this device under normal operation will typically be about 101 mW (60 mW quiescent power
+ 33 mW reference ladder power + 8 mW due to 1 TTL loan on each digital output. The values for maximum power dissipation listed above will be reached only when
the ADC1175 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is re-
versed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5kresistor. Machine model is 220 pf discharged through ZERO .
Note 6: See AN450, Surface Mounting Methods and Their Effect on Product Reliability, or the section entitled Surface Mountfound in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or to 500 mV below GND will not damage this device. However, errors
in the A/D conversion can occur if the input goes above VDD or below GND by more than 50 mV. As an example, if AVDD is 4.75VDC, the full-scale input voltage must
be 4.80VDC to ensure accurate conversions.
DS100092-10
Note 8: To guarantee accuracy, it is required that AVDD and DVDD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.
Note 9: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
Level).
Note 10: At least two clock cycles must be presented to the ADC1175 after power up. See Section 4.0 for details.
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ADC1175CIJMX pdf, datenblatt
Applications Information (Continued)
DS100092-14
FIGURE 4. Better defining the ADC Reference Voltage. Self-bias is still used, but the reference voltages are trimmed
by providing a small trim current with the operational amplifiers.
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