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PDF ADC1175-50CIJMX Data sheet ( Hoja de datos )
| Número de pieza | ADC1175-50CIJMX | |
| Descripción | 8-Bit/ 50 MSPS/ 125 mW A/D Converter | |
| Fabricantes | National Semiconductor | |
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January 2000
ADC1175-50
8-Bit, 50 MSPS, 125 mW A/D Converter
General Description
The ADC1175-50 is a low power, 50 MSPS analog-to-digital
converter that digitizes signals to 8 bits while consuming just
125 mW (typ). The ADC1175-50 uses a unique architecture
that achieves 6.8 Effective Bits and 25 MHz input and
50 MHz clock frequency. Output formatting is straight binary
coding.
The excellent DC and AC characteristics of this device, to-
gether with its low power consumption and +5V single supply
operation, make it ideally suited for many video and imaging
applications, including use in portable equipment. Further-
more, the ADC1175-50 is resistant to latch-up and the out-
puts are short-circuit proof. The top and bottom of the
ADC1175-50’s reference ladder is available for connections,
enabling a wide range of input possibilities. The low input ca-
pacitance (7 pF, typical) makes this device easier to drive
than conventional flash converters and the power down
mode reduces power consumption to less than 5 mW.
The ADC1175-50 is offered in SOIC (EIAJ) and TSSOP. It is
designed to operate over the commercial temperature range
of −20˚C to +75˚C.
Features
n Internal Track-and-Hold function
n Single +5V operation
n Internal reference bias resistors
n Industry standard pinout
n Power-down mode (<5 mW)
Key Specifications
n Resolution
8 Bits
n Maximum Sampling Frequency
50 MSPS (min)
n THD
54 dB (typ)
n DNL
0.7 LSB (typ)
n ENOB @ fIN = 25 MHz
n Guaranteed No Missing Codes
6.8 Bits (typ)
n Differential Phase
0.5˚ (typ)
n Differential Gain
1.0% (typ)
n Power Consumption
125 mW (typ), 190 mW (max)
(Excluding Reference Current)
Applications
n Digital Still Cameras
n CCD Imaging
n Electro-Optics
n Medical Imaging
n Communications
n Video Digitization
n Digital Television
n Multimedia
Connection Diagram
Ordering Information
ADC1175-50CIJM
ADC1175-50CIJMX
ADC1175-50CIMT
ADC1175-50CIMTX
DS100896-1
SOIC (EIAJ)
SOIC (EIAJ) (tape and reel)
TSSOP
TSSOP (tape and reel)
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS100896
www.national.com
1 page  
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (AVDD, DVDD)
Voltage on Any Input or Output Pin
Reference Voltage (VRT, VRB)
CLK, PD Voltage Range
Digital Output Voltage (VOH, VOL)
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at TA = 25˚C
6.5V
−0.3V to +6.5V
AVDD to VSS
−0.5 to (AVDD +0.5V)
VDD to VSS
±25 mA
±50 mA
See (Note 4)
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
Soldering Temperature, Infrared,
(10 sec.) (Note 6)
Storage Temperature
Short Circuit Duration
(Single High Output to Ground)
2000V
250V
300˚C
−65˚C to +150˚C
1 Second
Operating Ratings (Notes 1, 2)
Operating Temperature Range
Supply Voltage (AVDD, DVDD)
AVDD − DVDD
Ground Difference |DVSS–AVSS|
Upper Reference Voltage (VRT)
Lower Reference Voltage (VRB)
VIN Voltage Range
−20˚C ≤ TA ≤ +75˚C
+4.75V to +5.25V
<0.5V
0V to 100 mV
1.0V to VDD
0V to 4.0V
VRB to VRT
Converter Electrical Characteristics
The following specifications apply for AVDD = DVDD =
50 MHz at 50% duty cycle. Boldface limits apply for
+5.0
TA =
VDC,
TMIN
PD
to
= 0V,
TMAX;
VRT = +2.6V,
all other limits
VTRAB==205.˚6CV(,NCoLte=s
20 pF,
7, 8).
fCLK
=
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
DC ACCURACY
INL
DNL
Integral Non Linearity Error
Differential Non-Linearity
VIN = 0.6V to 2.6V
VIN = 0.6V to 2.6V
±0.8
+0.7
−0.7
±1.95
+1.75
−1.0
LSB (max)
LSB (max)
LSB (min)
Resolution for No Missing
Codes
8 Bits
EOT Top Offset Voltage
EOB Bottom Offset Voltage
VIDEO ACCURACY
−12 mV
+10 mV
DP Differential Phase Error
fIN = 4.43 MHz Modulated Ramp
DG Differential Gain Error
fIN = 4.43 MHz Modulated Ramp
ANALOG INPUT AND REFERENCE CHARACTERISTICS
0.5
1.0
deg
%
VIN Input Range
CIN VIN Input Capacitance
RIN RIN Input Resistance
BW Full Power Bandwidth
VIN = 1.5V
+0.7 Vrms
2.0 VRB V (min)
VRT V (max)
(CLK LOW)
4
pF
(CLK HIGH)
7
>1
pF
MΩ
120 MHz
RRT
RREF
Top Reference Resistor
Reference Ladder Resistance
VRT to VRB
320 Ω
270
200
350
Ω (min)
Ω (max)
RRB
IREF
Bottom Reference Resistor
Reference Ladder Current
VRT = VRTS, VRB = VRBS
VRT = VRTS, VRB = AVSS
80 Ω
5.4 mA (min)
7
10.8 mA (max)
6.1 mA (min)
8
12.3 mA (max)
VRT
Reference Top Self Bias
Voltage
VRT Connected to VRTS, VRB
Connected to VRBS
VRB
Reference Bottom Self Bias
Voltage
VRT Connected to VRTS, VRB
Connected to VRBS
2.6 V (min)
V (max)
0.6 0.55 V (min)
0.70 V (max)
5 www.national.com
5 Page 
Applications Information (Continued)
and 7 pF when the clock is high. Since a dynamic capaci-
tance is more difficult to drive than is a fixed capacitance,
choose an amplifier that can drive this type of load. The
CLC409 has been found to be an excellent device for driving
the ADC1175-50. Do not drive the input beyond the supply
rails. Figure 3 gives an example of driving circuitry.
DS100896-25
FIGURE 3. Driving the ADC1175-50. Choose an op-amp that can drive a dynamic capacitance.
2.0 REFERENCE INPUTS
The reference inputs VRT (Reference Top) and VRB (Refer-
ence Bottom) are the top and bottom of the reference ladder.
Input signals between these two voltages will be digitized to
8 bits. External voltages applied to the reference input pins
should be within the range specified in the Electrical Charac-
teristics table (1.0V to AVDD for VRT and 0V to (AVDD − 1.0V)
for VRB). Any device used to drive the reference pins should
be able to source sufficient current into the VRT pin and sink
sufficient current from the VRB pin.
The reference ladder can be self-biased by connecting VRT
to VRTS and connecting the VRB to VRBS to provide top and
bottom reference voltages of approximately 2.6V and 0.6V,
respectively, with VCC = 5.0V. This connection is shown in
Figure 3. If VRT and VRTS are tied together, but VRB is tied to
analog ground, a top reference voltage of approximately
2.3V is generated. The top and bottom of the ladder should
be bypassed with 10 µF tantalum capacitors located close to
the reference pins.
The reference self-bias circuit of Figure 3 is very simple and
the performance is adequate for many applications. Better
linearity performance can generally be achieved by driving
the reference pins with a low impedance source.
By forcing a little current into or out of the top and bottom of
the ladder, as shown in Figure 4, the top and bottom refer-
ence voltages can be trimmed and performance improved
over the self-bias method of Figure 3. The resistive divider at
the amplifier inputs can be replaced with potentiometers, if
desired. The LMC662 amplifier shown was chosen for its low
offset voltage and low cost. Note that a negative power sup-
ply is needed for these amplifiers as the lower one may be
required to go slightly negative to force the required refer-
ence voltage.
If reference voltages are desired that are more than a few
tens of millivolts from the self-bias values, the circuit of Fig-
ure 5 will allow forcing the reference voltages to whatever
levels are desired. This circuit provides the best performance
because of the low source impedance of the transistors.
Note that the VRTS and VRBS pins are left floating.
To minimize noise effects and ensure accurate conversions,
the total reference voltage range (VRT − VRB) should be a
minimum of 1.0V and a maximum of about 2.8V.
The ADC1175-50 is designed to operate with top and bottom
references of 2.6V and 0.6V, respectively. However, it will
function with reduced performance with a top reference volt-
age as high as AVDD.
11 www.national.com
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADC1175-50CIJMX.PDF ] | |
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