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PDF ADC1173CIJMX Data sheet ( Hoja de datos )

Número de pieza ADC1173CIJMX
Descripción 8-Bit/ 3-Volt/ 15MSPS/ 33mW A/D Converter
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! ADC1173CIJMX Hoja de datos, Descripción, Manual

February 1999
ADC1173
8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter
General Description
The ADC1173 is a low power, 15 MSPS analog-to-digital
converter that digitizes signals to 8 bits while consuming just
33 mW of power (typ). The ADC1173 uses a unique architec-
ture that achieves 7.6 Effective Bits. Output formatting is
straight binary coding.
The excellent DC and AC characteristics of this device, to-
gether with its low power consumption and +3V single supply
operation, make it ideally suited for many video, imaging and
communications applications, including use in portable
equipment. Furthermore, the ADC1173 is resistant to latchup
and the outputs are short-circuit proof. The top and bottom of
the ADC1173’s reference ladder is available for connections,
enabling a wide range of input possibilities.
The ADC1173 is offered in SOIC (EIAJ) and TSSOP. It is de-
signed to operate over the commercial temperature range of
-20˚C to +75˚C.
Features
n Internal Sample-and-Hold Function
n Single +3V Operation
n Internal Reference Bias Resistors
n Industry Standard Pinout
n TRI-STATE® Outputs
Key Specifications
n Resolution
8 Bits
n Maximum Sampling Frequency
15 MSPS (min)
n THD
−56 dB (typ)
n DNL
±0.8 LSB (max)
n ENOB at 3.58 MHz Input
7.6 Bits (typ)
n Guaranteed No Missing Codes
n Differential Phase
0.5 Degree (max)
n Differential Gain
1.5% (typ)
n Power Consumption
33mW (typ)
(excluding reference current)
Applications
n Video Digitization
n Digital Still Cameras
n Set Top Boxes
n Camcorders
n Personal Computer Video
n Digital Television
n CCD Imaging
n Electro-Optics
Ordering Information
ADC1173CIJM
ADC1173CIJMX
ADC1173CIMTC
ADC1173CIMTCX
SOIC (EIAJ)
SOIC (EIAJ) (tape & reel)
TSSOP
TSSOP (tape & reel)
Pin Configuration
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100890
DS100890-1
www.national.com

1 page




ADC1173CIJMX pdf
Converter Electrical Characteristics (Continued)
The following specifications apply for AVDD =
at 50% duty cycle. Boldface limits apply for
DTVAD=D
= +3.0VDC, OE =
TMIN to TMAX; all
0V, VRT =
other limits
T+2A.0=V2, 5V˚CRB(N=o0teVs,
CL =
7, 8)
20
pF,
fCLK
=
15MHz
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
Units
Analog Input and Reference Characteristics
VRT -
VRB
Reference Voltage Delta
Power Supply Characteristics
1.0 V(min)
2
VA V(max)
IADD
IDDD
IAVDD +
IDVDD
Analog Supply Current
Digital Supply Curretn
Total Operating Current
DVDD = AVDD = 3.6V
DVDD = AVDD = 3.6V
DVDD AVDD = 3.6V,
DVDD = AVDD = 3.6V, CLK Low
(Note 10)
6.8
2.3
9.1 11
5.8
mA
mA
mA
mA
Power Consumption
CLK, OE Digital Input Characteristics
DVDD = AVDD = 3.6V
33 40
mW
VIH Logical High Input Voltage
VIL Logical Low Input Voltage
IIH Logical High Input Current
IIL Logic Low Input Current
CIN Logic Input Capacitance
Digital Output Characteristics
DVDD = AVDD = 3.6V
DVDD = AVDD = 3.6V
VIH = DVDD = AVDD = 3.6V
VIL = 0V, DVDD = AVDD = 3.6V
2.2 V (min)
0.8 V (max)
5 µA
−5 µA
5 pF
VOH High Level Output Voltage
VOL Low Level Output Voltage
IOZH,
IOZL
Tri-State®Leakage Current
AC Electrical Characteristics
DVDD = 2.7V, IOH = −360µA
DVDD = 2.7V, IOH = −1.1mA
DVDD = 2.7V, IOL = 1.6mA
DVDD = 3.6V, OE = DVDD,
VOL = 0V or VOH = DVDD
2.4 V(min)
2.1 1.9 V(min)
0.32 0.6 V(max)
±20 µA
fC1
fC2
tOD−0
tOD−1
Maximum Conversion Rate
Minimum Conversion Rate
Output Delay
Output Delay
Pipline Delay (Latency)
CLK high to low data valid
CLK low to high data valid
20 15 MHz(min)
1 MHz
28 ns(max)
24 ns(max)
2.5
Clock
Cycles
tDS
tAJ
tOH
tEN
tDIS
ENOB
SINAD
SNR
SFDR
THD
Sampling (Aperture) Delay
Aperture Jitter
Output Hold Time
OE Low to Data Valid
OE High to High Z State
Effective Number of Bits
Signal-to- Noise & Distortion
Signal-to-Noise Ratio
Spurious Free Dynamic
Range
Total Harmonic Distortion
CLK low to acquissition of data
CLK high to data invalid
Loaded as in Figure 2
Loaded as in Figure 2
fIN = 1.31 MHz
fIN = 3.58 MHz
fIN = 7.5 MHz
fIN = 1.31 MHz
fIN = 3.58 MHz
fIN = 7.5 MHz
fIN = 1.31 MHz
fIN = 3.58 MHz
fIN = 7.5 MHz
fIN = 1.31 MHz
fIN = 3.58 MHz
fIN = 7.5 MHz
fIN = 1.31 MHz
fIN = 3.58 MHz
fIN = 7.5 MHz
3 ns
30 ps rms
15 ns
22 ns
12 ns
7.7
7.6 7.0 Bits (min)
7.4
49
47.7
46.5
43 dB(min)
49
48.7
48.0
44 dB(min)
65
55 dB
51
−62
−54 dB
−51
5 www.national.com

5 Page





ADC1173CIJMX arduino
Applications Information (Continued)
DS100890-13
FIGURE 3. Simple, Low Component Count, Self -Bias Reference application. Because of resistor tolerances, the
reference voltages can vary by as much as 6%. Choose an amplifier that can drive a dynamic capacitance (see text).
11 www.national.com

11 Page







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