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PDF ADC10D020EVAL Data sheet ( Hoja de datos )
| Número de pieza | ADC10D020EVAL | |
| Descripción | Dual 10-Bit/ 20 MSPS/ 150 mW A/D Converter | |
| Fabricantes | National Semiconductor | |
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April 2002
ADC10D020
Dual 10-Bit, 20 MSPS, 150 mW A/D Converter
General Description
The ADC10D020 is a dual low power, high performance
CMOS analog-to-digital converter that digitizes signals to 10
bits resolution at sampling rates up to 30 MSPS while con-
suming a typical 150 mW from a single 3.0V supply. No
missing codes is guaranteed over the full operating tempera-
ture range. The unique two stage architecture achieves 9.5
Effective Bits over the entire Nyquist band at 20 MHz sample
rate. An output formatting choice of straight binary or 2’s
complement coding and a choice of two gain settings eases
the interface to many systems. Also allowing great flexibility
of use is a selectable 10-bit multiplexed or 20-bit parallel
output mode. An offset correction feature minimizes the off-
set error.
To ease interfacing to most low voltage systems, the digital
output power pins of the ADC10D020 can be tied to a
separate supply voltage of 1.5V to 3.6V, making the outputs
compatible with other low voltage systems. When not con-
verting, power consumption can be reduced by pulling the
PD (Power Down) pin high, placing the converter into a low
power state where it typically consumes less than 1 mW and
from which recovery is less than 1 ms. Bringing the STBY
(Standby) pin high places the converter into a standby mode
where power consumption is about 27 mW and from which
recovery is 800 ns.
The ADC10D020’s speed, resolution and single supply op-
eration makes it well suited for a variety of applications,
including high speed portable applications.
Operating over the industrial (−40˚ ≤ TA ≤ +85˚C) tempera-
ture range, the ADC10D020 is available in a 48-pin TQFP. An
evaluation board is available to ease the design effort.
Features
n Internal sample-and-hold
n Internal reference capability
n Dual gain settings
n Offset correction
n Selectable straight binary or 2’s complement output
n Multiplexed or parallel output bus
n Single +2.7V to 3.6V operation
n Power down and standby modes
Key Specifications
n Resolution
10 Bits
n Conversion Rate
20 MSPS
n ENOB
9.5 Bits (typ)
n DNL
0.35 LSB (typ)
n Conversion Latency Parallel Outputs 2.5 Clock Cycles
— Multiplexed Outputs, I Data Bus 2.5 Clock Cycles
— Multiplexed Outputs, Q Data Bus
3 Clock Cycles
n PSRR
90 dB
n Power Consumption — Normal Operation 150 mW (typ)
— Power Down Mode
<1 mW (typ)
— Fast Recovery Standby Mode
27 mW (typ)
Applications
n Digital Video
n CCD Imaging
n Portable Instrumentation
n Communications
n Medical Imaging
n Ultrasound
© 2002 National Semiconductor Corporation DS200255
www.national.com
1 page  
Pin Descriptions and Equivalent Circuits (Continued)
Pin No.
33
Symbol
CLK
2 OS
31 OC
32 OF
34 STBY
35 PD
36 GAIN
8 thru 27 I0–I9 and Q0–Q9
28 I/Q
40, 41
VA
Equivalent Circuit
Description
Digital clock input for both converters. The analog inputs are
sampled on the falling edge of this clock input.
Output Bus Select. With this pin at a logic high, both the “I”
and the “Q” data are present on their respective 10-bit output
buses (Parallel mode of operation). When this pin is at a logic
low, the “I” and “Q” data are multiplexed onto the “I” output
bus and the “Q” output lines all remain at a logic low
(multiplexed mode).
Offset Correct pin. A low-to-high transition on this pin initiates
an independent offset correction sequence for each converter,
which takes 34 clock cycles to complete. During this time 32
conversions are taken and averaged. The result is subtracted
from subsequent conversions. Each input pair should have 0V
differential value during this entire 34 clock period.
Output Format pin. When this pin is LOW the output format is
Straight Binary. When this pin is HIGH the output format is 2’s
complement. This pin may be changed asynchronously, but
this will result in errors for one or two conversions.
Standby pin. The device operates normally with a logic low on
this and the PD (Power Down) pin. With this pin at a logic
high and the PD pin at a logic low, the device is in the
standby mode where it consumes just 27 mW of power. It
takes just 800 ns to come out of this mode after the STBY pin
is brought low.
Power Down pin that, when high, puts the converter into the
Power Down mode where it consumes less than 1 mW of
power. It takes less than 1 ms to recover from this mode after
the PD pin is brought low. If both the STBY and PD pins are
high simultaneously, the PD pin dominates.
This pin sets the internal signal gain at the inputs to the
ADCs. With this pin low the full scale differential input
peak-to-peak signal is equal to VREF. With this pin high the
full scale differential input peak-to-peak signal is equal to 2 x
VREF.
3V TTL/CMOS-compatible Digital Output pins that provide the
conversion results of the I and Q inputs. I0 and Q0 are the
LSBs, I9 and Q9 are the MSBs. Valid data is present just after
the rising edge of the CLK input in the Parallel mode. In the
multiplexed mode, I-channel data is valid on I0 through I9
when the I/Q output is high and the Q-channel data is valid
on I0 through I9 when the I/Q output is low.
Output data valid signal. In the multiplexed mode, this pin
transitions from low to high when the data bus transitions
from Q-data to I-data, and from high to low when the data bus
transitions from I-data to Q-data. In the Parallel mode, this pin
transitions from low to high as the output data changes.
Positive analog supply pin. This pin should be connected to a
quiet voltage source of +2.7V to +3.6V. VA and VD should
have a common supply and be separately bypassed with
10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors.
5 www.national.com
5 Page 
AC Electrical Characteristics OS = High (Parallel Mode) (Continued)
20025506
Note 8: Typical figures are at TJ = 25˚C, and represent most likely parametric norms.
Note 9: Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Performance is guaranteed only at VREF = 1.0V and a clock duty cycle
of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are performed and limits guaranteed with
clock low and high levels of 0.3V and VD − 0.3V, respectively.
Note 10: IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output pins, the supply
voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR = VDR (CO x fO + C1 x f1 + ... + C9 x f9) where VDR is the output driver
power supply voltage, Cn is the total capacitance on the output pin, and fn is the average frequency at which that pin is toggling.
Timing Diagrams
ADC10D020 Timing Diagram for Multiplexed Mode
20025508
11 www.national.com
11 Page | ||
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| PDF Descargar | [ Datasheet ADC10D020EVAL.PDF ] | |
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