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ADC10832 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC10832
Beschreibung 10-Bit Plus Sign Serial I/O A/D Converters with MUX/ Sample/Hold and Reference
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 30 Seiten
ADC10832 Datasheet, Funktion
December 1994
ADC10831 ADC10832 ADC10834 ADC10838
10-Bit Plus Sign Serial I O A D Converters
with MUX Sample Hold and Reference
General Description
This series of CMOS 10-bit plus sign successive approxima-
tion A D converters features versatile analog input multi-
plexers sample hold and a 2 5V band-gap reference The
1 2 4 or 8-channel multiplexers can be software configured
for single-ended or differential mode of operation
An input sample hold is implemented by a capacitive refer-
ence ladder and sampled-data comparator This allows the
analog input to vary during the A D conversion cycle
In the differential mode valid outputs are obtained even
when the negative inputs are greater than the positive be-
cause of the 10-bit plus sign output data format
The serial I O is configured to comply with the NSC
MICROWIRETM serial data exchange standard for easy in-
terface to the COPSTM and HPCTM families of controllers
and can easily interface with standard shift registers and
microprocessors
Applications
Y Medical instruments
Y Remote instrumentation
Y Test equipment
Features
Y b5V to a5V analog voltage range with g5V supplies
Y Serial I O (MICROWIRE compatible)
Y 1 2 4 or 8-channel differential or single-ended
multiplexer
Y Software or hardware power down
Y Analog input sample hold function
Y Ratiometric or Absolute voltage referencing
Y No zero or full scale adjustment required
Y No missing codes over temperature
Y TTL MOS input output compatible
Y Standard DIP and SO packages
Key Specifications
Y Resolution
Y Dual supply
Y Power dissipation
Y In power down mode
Y Conversion time
Y Sampling rate
Y Band-gap reference
10 bits plus sign
g5V
59 mW (Max)
33 mW
5 ms (Max)
74 kHz (Max)
2 5V g2% (Max)
ADC10838 Simplified Block Diagram
COPSTM HPCTM and MICROWIRETM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 11391
TL H 11391 – 1
RRD-B30M75 Printed in U S A






ADC10832 Datasheet, Funktion
Electrical Characteristics (Continued)
The following specifications apply for Va e AVa e DVa e a5 0 VDC VREFa e a4 096 VDC VREFb e VIN e GND
Vb e b5 0 VDC and fCLK e 2 5 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX
all other limits TA e TJ e a25 C (Note 16)
Symbol
Parameter
Conditions
Typical
Limits
(Note 11) (Note 12)
Units
(Limits)
AC CHARACTERISTICS
fCLK
Clock Frequency
3 0 2 5 MHz(max)
5 kHz(min)
Clock Duty Cycle
40 %(min)
60 %(max)
tC Conversion Time
12 12 Clock
Cycles
5 5 ms(max)
tA Acquisition Time
4 5 4 5 Clock
Cycles
2 2 ms(max)
tSCS
CS Set-Up Time Set-Up Time from Falling Edge of
CS to Rising Edge of Clock
14
(1 tCLK
b 14 ns)
30
(1 tCLK
b30 ns)
ns(min)
(max)
tSDI DI Set-Up Time Set-Up Time from Data Valid on
DI to Rising Edge of Clock
16 25 ns(min)
tHDI DI Hold Time Hold Time of DI Data from Rising
Edge of Clock to Data not Valid on DI
2 25 ns(min)
tAT DO Access Time from Rising Edge of CLK When
CS is ‘‘Low’’ during a Conversion
30 50 ns(min)
tAC DO or SARS Access Time from CS Delay from
Falling Edge of CS to Data Valid on DO or SARS
30 70 ns(max)
tDSARS
Delay from Rising Edge of Clock to Falling Edge of
SARS when CS is ‘‘Low’’
100
200
ns(max)
tHDO
DO Hold Time Hold Time of Data on DO after
Falling Edge of Clock
20 45 ns(max)
tAD DO Access Time from Clock Delay from Falling
Edge of Clock to Valid Data of DO
40 80 ns(max)
t1H t0H
Delay from Rising Edge of CS to DO or SARS
TRI-STATE
40 50 ns(max)
tDCS
Delay from Falling Edge of Clock to Falling Edge of
CS
20 30 ns(min)
tCS(H)
CS ‘‘HIGH’’ Time for A D Reset after Reading of
Conversion Result
1 CLK
1 CLK cycle(min)
tCS(L)
ADC10731 Minimum CS ‘‘Low’’ Time to Start a
Conversion
1 CLK
1 CLK cycle(min)
tSC Time from End of Conversion to CS Going ‘‘Low’’
tPD Delay from Power-Down command to 10% of
Operating Current
5 CLK
1
5 CLK
cycle(min)
ms
tPC Delay from Power-Up Command to Ready to Start
a New Conversion
10 ms
CIN
COUT
Capacitance of Logic Inputs
Capacitance of Logic Outputs
7 pF
12 pF
6

6 Page









ADC10832 pdf, datenblatt
TRI-STATE Test Circuits and Waveforms
TL H 11391–12
Timing Diagrams
TL H 11391–14
TL H 11391 – 13
TL H 11391 – 15
FIGURE 2 DI Timing
TL H 11391 – 16
FIGURE 3 DO Timing
12
TL H 11391 – 17

12 Page





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