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PDF ADC10462 Data sheet ( Hoja de datos )
| Número de pieza | ADC10462 | |
| Descripción | 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 1999
ADC10461/ADC10462/ADC10464
10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
General Description
Using an innovative, patented multistep* conversion tech-
nique, the 10-bit ADC10461, ADC10462, and ADC10464
CMOS analog-to-digital converters offer sub-microsecond
conversion times yet dissipate a maximum of only 235 mW.
The ADC10461, ADC10462, and ADC10464 perform a
10-bit conversion in two lower-resolution “flashes”, thus
yielding a fast A/D without the cost, power dissipation, and
other problems associated with true flash approaches. Dy-
namic performance (THD, S/N) is guaranteed. The
ADC10461 is pin-compatible with the ADC1061 but much
faster, thus providing a convenient upgrade path for the
ADC1061.
The analog input voltage to the ADC10461, ADC10462, and
ADC10464 is sampled and held by an internal sampling cir-
cuit. Input signals at frequencies from dc to over 200 kHz
can therefore be digitized accurately without the need for an
external sample-and-hold circuit.
The ADC10462 and ADC10464 include a “speed-up” pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 350 ns with
only a small increase in linearity error.
For ease of interface to microprocessors, the ADC10461,
ADC10462, and ADC10464 have been designed to appear
as a memory location or I/O port without the need for exter-
nal interface logic.
Features
n Built-in sample-and-hold
n Single +5V supply
n 1, 2, or 4-input multiplexer options
n No external clock required
n Speed adjust pin for faster conversions (ADC10462 and
ADC10464)
Key Specifications
n Conversion time to 10 bits
n Sampling Rate
n Low power dissipation
n Total harmonic distortion (50 kHz)
n No missing codes over temperature
600 ns typical
800 kHz
235 mW (max)
−60 dB (max)
Applications
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
Note: *U.S. Patent Number 4918449
Ordering Information
Industrial Temp Range
(−40˚C ≤ TA ≤ +85˚C)
ADC20461CIWM
ADC20462CIWM
ADC20464CIWM
Package
M20B Small Outline
M24B Small Outline
M28B Small Outline
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011108
www.national.com
1 page  
AC Electrical Characteristics (Continued)
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. In most cases,
the maximum derated power dissipation will be reached only during fault conditions. For these devices, TJMAX for a board-mounted device can be found from the
tables below:
Device
ADC20461CIWM
ADC20462CIWM
ADC20464CIWM
θJA (˚C/W)
85
82
78
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National Semicon-
ductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals represent most likely parametric norm.
Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if tSH is shorter than the value specified. See curves of Accuracy vs tSH.
5 www.national.com
5 Page 
Applications Information (Continued)
must be low to enable S /H or RD. CS is internally “ANDed”
with S /H and RD; the input voltage is sampled when CS and
S /H are low, and data is read when CS and RD are low. INT
is reset high on the rising edge of RD.
TABLE 1. Input Multiplexer Programming
ADC10464
S1 S0 Channel
00
VIN0
01
VIN1
10
VIN2
11
VIN3
TABLE 2. Input Multiplexer Programming
ADC10462
S0 Channel
0 VIN0
1 VIN1
Mode 2
In Mode 2, also called “RD mode”, the S /H and RD pins are
tied together. A conversion is initiated by pulling both pins
low. The A/D converter samples the input voltage and
causes the coarse comparators to become active. An inter-
nal timer then terminates the coarse conversion and begins
the fine conversion. 850 ns (typical) after S /H and RD are
pull low, INT goes low, indicating that the conversion is com-
pleted. Approximately 20 ns later the data appearing on the
TRI-STATE output pins will be valid. Note that data will ap-
pear on these pins throughout the conversion, but until INT
goes low the data at the output pins will be the result of the
previous conversion.
2.0 REFERENCE CONSIDERATIONS
The ADC10461, ADC10462, and ADC10464 each have two
reference inputs. These inputs, VREF+ and VREF−, are fully
differential and define the zero to full-scale range of the input
signal. The reference inputs can be connected to span the
entire supply voltage range (VREF− = 0V, VREF+ = VCC) for
ratiometric applications, or they can be connected to differ-
ent voltages (as long as they are between ground and VCC)
when other input spans are required. Reducing the overall
VREF span to less than 5V increases the sensitivity of the
converter (e.g., if VREF = 2V, then 1 LSB = 1.953 mV). Note,
however, that linearity and offset errors become larger when
lower reference voltages are used. See the Typical Perfor-
mance Curves for more information. For this reason, refer-
ence voltages less than 2V are not recommended.
In most applications, VREF− will simply be connected to
ground, but it is often useful to have an input span that is off-
set from ground. This situation is easily accommodated by
the reference configuration used in the ADC10461,
ADC10462, and ADC10464. VREF− can be connected to a
voltage other than ground as long as the voltage source con-
nected to this pin is capable of sinking the converter’s refer-
ence current (12.5 mA Max @ VREF = 5V). If VREF− is con-
nected to a voltage other than ground, bypass it with multiple
capacitors.
Since the resistance between the two reference inputs can
be as low as 400Ω, the voltage source driving the reference
inputs should have low output impedance. Any noise on ei-
ther reference input is a potential cause of conversion errors,
so each of these pins must be supplied with a clean, low
noise voltage source. Each reference pin should be by-
passed with a 10 µF tantalum and a 0.1 µF ceramic.
3.0 THE ANALOG INPUT
The ADC10461, ADC10462, and ADC10464 sample the
analog input voltage once every conversion cycle. When this
happens, the input is briefly connected to an impedance ap-
proximately equal to 600Ω in series with 35 pF.
Short-duration current spikes can therefore be observed at
the analog input during normal operation. These spikes are
normal and do not degrade the converter’s performance.
Large source impedances can slow the charging of the sam-
pling capacitors and degrade conversion accuracy. There-
fore, only signal sources with output impedances less than
500Ω should be used if rated accuracy is to be achieved at
the minimum sample time (250 ns maximum). If the sam-
pling time is increased, the source impedance can be larger.
If a signal source has a high output impedance, its output
should be buffered with an operational amplifier. The opera-
tional amplifier’s output should be well-behaved when driving
a switched 35 pF/600Ω load. Any ringing or voltage shifts at
the op amp’s output during the sampling period can result in
conversion errors.
Correct conversion results will be obtained for input voltages
greater than GND − 50 mV and less than V+ + 50 mV. Do not
allow the signal source to drive the analog input pin more
than 300 mV higher than AVCC and DVCC, or more than 300
mV lower than GND. If an analog input pin is forced beyond
these voltages, the current flowing through the pin should be
limited to 5 mA or less to avoid permanent damage to the IC.
The sum of all the overdrive currents into all pins must be
less than 20 mA. When the input signal is expected to extend
more than 300 mV beyond the power supply limits, some
sourt of protection scheme should be used. A simple network
using diodes and resistors is shown in Figure 4.
11 www.national.com
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ADC10462.PDF ] | |
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