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PDF ADC1031 Data sheet ( Hoja de datos )
| Número de pieza | ADC1031 | |
| Descripción | ADC1031/ADC1034/ADC1038 10-Bit Serial I/O A/D Converters with Analog Multiplexer and Track/Hold Function | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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January 1995
ADC1031 ADC1034 ADC1038 10-Bit Serial
I O A D Converters with Analog Multiplexer
and Track Hold Function
General Description
The ADC1031 ADC1034 and ADC1038 are 10-bit succes-
sive approximation A D converters with serial I O The seri-
al input for the ADC1034 and ADC1038 controls a single-
ended analog multiplexer that selects one of 4 input chan-
nels (ADC1034) or one of 8 input channels (ADC1038) The
ADC1034 and ADC1038 serial output data can be config-
ured into a left- or right-justified format
An input track hold is implemented by a capacitive refer-
ence ladder and sampled-data comparator This allows the
analog input to vary during the A D conversion cycle
Separate serial I O and conversion clock inputs are provid-
ed to facilitate the interface to various microprocessors
Applications
Y Engine control
Y Process control
Y Instrumentation
Y Test equipment
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRETM is a trademark of National Semiconductor Corporation
Features
Y Serial I O (MICROWIRETM compatible)
Y Separate asynchronous converter clock and serial data
I O clock
Y Analog input track hold function
Y Ratiometric or absolute voltage referencing
Y No zero or full scale adjustment required
Y 0V to 5V analog input range with single 5V power
supply
Y TTL MOS input output compatible
Y No missing codes
Key Specifications
Y Resolution
10 bits
Y Total unadjusted error
g1 LSB (max)
Y Single supply
5V g5%
Y Power dissipation
20 mW (max)
Y Max conversion time (fC e 3 MHz)
13 7 ms (max)
Y Serial data exchange time (fS e 1 MHz) 10 ms (max)
Connection Diagrams
Dual-In-Line and SO Packages
TL H 10556–4
Top View
ADC1031 In NS Package N08E
Ordering Information
TL H 10556 – 3
Top View
ADC1034 In NS Packages
J16A M16B or N16E
Industrial b40 C s TA s a85 C
ADC1031CIN
ADC1034CIN
ADC1034CIWM
ADC1038CIN
ADC1038CIWM
Military b55 C s TA s a125 C
ADC1034CMJ
ADC1038CMJ
Package
N08E
N16E
M16B
N20A
M20B
Package
J16A
J20A
TL H 10556 – 2
Top View
ADC1038 In NS Packages
J20A M20B or N20A
C1995 National Semiconductor Corporation TL H 10556
RRD-B30M75 Printed in U S A
1 page  
Typical Performance Characteristics
Power Supply Current
(ICC) vs CCLK
Power Supply Current (ICC)
vs Ambient Temperature
Reference Current (IREF)
vs Ambient Temperature
Linearity Error vs
CCLK Frequency
Linearity Error vs
Ambient Temperature
Linearity Error vs
Reference Voltage
Zero Error vs
Reference Voltage
TL H 10556 – 5
5
5 Page 
2 0 Functional Description (Continued)
occur there will be an uncertainty as to which SCLK rising
edge will clock in the first bit of data CS must remain low
during the complete I O exchange Also OE needs to be
low if data from the previous conversion needs to be ac-
cessed
2 3 1 CS LOW CONTINUOUSLY
Another way to accomplish synchronous serial communica-
tion is to tie CS low continuously and use SARS and SCLK to
synchronize the serial data exchange SCLK can be disabled
low during the conversion time and enabled after SARS
goes low With CS low during the conversion time a zero will
remain on DO until the conversion is completed Once the
conversion is complete the falling edge of SARS will shift
out on DO the MSB before SCLK is enabled This MSB
would be a leading zero if right-justified or D9 if left-justified
The rest of the data will be shifted out once SCLK is enabled
as discussed previously If CS goes high during the conver-
sion sequence DO is put into TRI-STATE and the conver-
sion result is not affected so long as CS remains high until
the end of the conversion
2 4 TYING SCLK and CCLK TOGETHER
SCLK and CCLK can be tied together The total conversion
time will increase because the maximum clock frequency is
now 1 MHz The timing diagrams and the serial I O ex-
change time (10 SCLK cycles) remain the same but the con-
version time (TC e 41 CCLK cycles) lengthens from a mini-
mum of 14 ms to a minimum of 41 ms In the case where CS
is low continuously since the applied clock cannot be dis-
abled SARS must be used to synchronize the data output
on DO and initiate a new conversion The falling edge of
SARS sends the MSB information out on DO The next ris-
ing edge of the clock shifts in MUX address bit A2 on DI
The following clock falling edge will clock the next data bit
of information out on DO A conversion will be started after
MUX addressing information has been loaded in (3 more
clocks) and the analog sampling time (4 5 clocks) has
elapsed The ADC1031 does not have SARS Therefore CS
cannot be left low continuously on the ADC1031
3 0 Analog Considerations
3 1 THE INPUT SAMPLE AND HOLD
The ADC1031 4 8’s sample hold capacitor is implemented
in its capacitive ladder structure After the channel address
is received the ladder is switched to sample the proper ana-
log input This sampling mode is maintained for 4 5 SCLK
cycles after the multiplexer addressing information is loaded
in For the ADC1031 4 8 the sampling of the analog input
starts on SCLK’s 4th rising edge
An acquisition window of 4 5 SCLK cycles is available to
allow the ladder capacitance to settle to the analog input
voltage Any change in the analog voltage before or after
the acquisition window will not effect the A D conversion
result
In the most simple case the ladder’s acquisition time is de-
termined by the Ron (9 kX) of the multiplexer switches the
CS1 (3 5 pF) and the total ladder (CL) and stray (CS2) capac-
itance (48 pF) For large source resistance the analog input
can be modeled as an RC network as shown in Figure 1
The values shown yield an acquisition time of about 3 ms for
10 bit accuracy with a zero to a full scale change in the
reading External source resistance and capacitance will
lengthen the acquisition time and should be accounted for
The curve ‘‘Signal to Noise Ratio vs Output Frequency’’
(Figure 2) gives an indication of the usable bandwidth of the
ADC1031 ADC1034 ADC1038 The signal to noise ratio of
an ideal A D is the ratio of the RMS value of the full scale
input signal amplitude to the value of the total error ampli-
tude (including noise) caused by the transfer function of the
A D An ideal 10 bit A D converter with a total unadjusted
error of 0 LSB would have a signal to noise ratio of about
62 dB which can be derived from the equation
S N e 6 02(N) a 1 8
where S N is in dB and N is the number of bits Figure 2
shows the signal to noise ratio vs input frequency of a typi-
cal ADC1031 4 8 with LSB total unadjusted error The
dotted lines show signal-to-noise ratios for an ideal (noise-
less) 10 bit A D with 0 LSB error and an A D with a 1 LSB
error
The sample-and-hold error specifications are included in the
error and timing specifications of the A D The hold step
and gain error sample hold specs are taken into account in
the ADC1031 4 8’s total unadjusted error specification
while the hold settling time is included in the A D’s maxi-
mum conversion time specification The hold droop rate can
be thought of as being zero since an unlimited amount of
time can pass between a conversion and the reading of
data However once the data is read it is lost and another
conversion is started
3 2 INPUT FILTERING
Due to the sampling nature of the analog input transients
will appear on the input pins They are caused by the ladder
capacitance and internal stray capacitance charging current
flowing into VIN These transients will not degrade the A D’s
performance if they settle out within the sampling window
This will occur if external source resistance is kept to a mini-
mum
TL H 10556 – 18
FIGURE 1 Analog Input Model
11
TL H 10556 – 19
FIGURE 2 ADC1031 4 8 Signal to
Noise Ratio vs Input Frequency
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ADC1031.PDF ] | |
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