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PDF ADC10221CIVT Data sheet ( Hoja de datos )
| Número de pieza | ADC10221CIVT | |
| Descripción | 10-Bit/ 15 MSPS/ 98 mW A/D Converter with Internal Sample and Hold | |
| Fabricantes | National Semiconductor | |
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January 2000
ADC10221
10-Bit, 15 MSPS, 98 mW A/D Converter with Internal
Sample and Hold
General Description
The ADC10221 is the first in a family of low power, high per-
formance CMOS analog-to-digital converters. It can digitize
signals to 10 bits resolution at sampling rates up to 20 MSPS
(15 MSPS guaranteed) while consuming a typical 98 mW
from a single 5V supply. Reference force and sense pins al-
low the user to connect an external reference buffer amplifier
to ensure optimal accuracy. The ADC10221 is guaranteed to
have no missing codes over the full operating temperature
range. The unique two stage architecture achieves 9.2 Effec-
tive Bits with a 10MHz input signal and a 20MHz clock fre-
quency. Output formatting is straight binary coding.
To ease interfacing to 3V systems, the digital I/O power pins
of the ADC10221 can be tied to a 3V power source, making
the outputs 3V compatible. When not converting, power con-
sumption can be reduced by pulling the PD (Power Down)
pin high, placing the converter into a low power standby
state, where it typically consumes less than 4 mW. The
ADC10221’s speed, resolution and single supply operation
make it well suited for a variety of applications in video, im-
aging, communications, multimedia and high speed data ac-
quisition. Low power, single supply operation ideally suit the
ADC10221 for high speed portable applications, and its
speed and resolution are ideal for charge coupled device
(CCD) input systems.
The ADC10221 comes in a space saving 32-pin TQFP and
operates over the industrial (−40˚C ≤ TA ≤ +85˚C) tempera-
ture range.
Features
n Internal Sample-and-Hold
n Single +5V Operation
n Low Power Standby Mode
n Guaranteed No Missing Codes
n TTL/CMOS or 3V Logic Input/Output Compatible
Key Specifications
n Resolution
n Conversion Rate
n ENOB 10 MHz Input,
20 MHz Clock
n DNL
n Power Consumption
n Low Power Standby Mode
10 Bits
20 MSPS (typ)
15 MSPS (min)
9.2 Bits (typ)
0.35 LSB (typ)
98 mW (typ)
<4 mW (typ)
Applications
n Digital Video
n Document Scanners
n Medical Imaging
n Electro-Optics
n Plain Paper Copiers
n CCD Imaging
Connection Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101038
DS101038-1
www.national.com
1 page  
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage (V = VA = VD)
6.5V
Voltage on Any I/O Pin
−0.3V to (VA or VD) +0.3V)
Input Current at Any Pin (Note 3)
±25mA
Package Input Current (Note 3)
±50mA
Package Dissipation at TA = 25˚C
ESD Susceptibility (Note 5)
See (Note 4)
Human Body Model
1500V
Machine Model
200V
Soldering Temp., Infrared, 10 sec. (Note 6)
300˚C
Storage Temperature
−65˚C to +150˚C
Operating Ratings(Notes 1, 2)
Operating Temperature
VA, VD Supply Voltage
VD I/O Supply Voltage
VIN Voltage Range
VREF + Voltage Range
VREF− Voltage Range
PD, CLK, OE Voltage
−40˚C ≤ TA ≤ +85˚C
+4.5V to +5.5V
+2.7V to 5.5V
1.3V to (VA-1.0V)
2.3V to (VA-1.0V)
1.3V to 3.0V
−0.3V to + 5.5V
Converter Electrical Characteristics
The following specifications
CL = 20pF, fCLK = 15 MHz,
apply
RS =
for VA = +5.0VDC, VD
25Ω. Boldface limits
= 5.0VDC,
apply for
VD
TA
=I/OTM=IN5t.o0VTDMCA,XV:RaEllF+oth=e+r 3li.m5VitsDCT,AV=RE2F5−˚C=(N+o1t.e5V7D) C,
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
Static Converter Characteristics
INL Integral Non-Linearity
±0.45
±1.0
LSB(max)
DNL
Differential-Non Linearity
±0.35
±0.85
LSB(max)
Resolution with No Missing
Codes
10 Bits
Zero Scale Offset Error
−6 mV(max)
Full-Scale Error
−6 mV(max)
Dynamic Converter Characteristics
ENOB
Effective Number of Bits
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
SNR
Signal-to-Noise Ratio
THD
SFDR
DG
DP
BW
Total Harmonic Distortion
Spurious Free Dynamic
Range
Differential Gain Error
Differential Phase Error
Overrange Output Code
Underrange Output Code
Full Power Bandwidth
fIN = 1.0 MHz
fIN = 4.43 MHz
fIN = 10 MHz, fCLK = 20 MHz
fIN = 1.0 MHz
fIN = 4.43 MHz
fIN = 10 MHz, fCLK = 20 MHz
fIN = 1.0 MHz
fIN = 4.43 MHz
fIN = 10 MHz, fCLK = 20 MHz
fIN = 1.0 MHz
fIN = 4.43 MHz
fIN = 10 MHz, fCLK = 20 MHz
fIN = 1.0 MHz
fIN = 4.43 MHz
fIN = 10 MHz, fCLK = 20 MHz
fIN = 4.43 MHz, fCLK = 17.72 MHz
fIN = 4.43 MHz, fCLK = 17.72 MHz
VIN > VREF+
VIN < VREF−
9.5 Bits
9.5 9.0 Bits(min)
9.2 Bits
59 dB
59 56 dB(min)
57 dB
60 dB
60 58 dB(min)
58 dB
−71 dB
−70 −59 dB(min)
−66 dB
74
72 60
68
dB
dB
dB
0.5 %
0.5 deg
1023
0
150 MHz
PSRR
Power Supply Rejection
Ratio
Change in Full Scale with 4.5V to
5.5V Supply Change
56
dB
Reference and Analog Input Characteristics
VIN Analog Input Range
1.3 V(min)
4.0 V(max)
CIN
Analog VIN Input
Capacitance
5 pF
IIN Input Leakage Current
10 µA
5 www.national.com
5 Page 
Applications Information
1.0 THE ANALOG INPUT
The analog input of the ADC10221 is a switch (transmission
gate) followed by a switched capacitor amplifier. The capaci-
tance seen at the input changes with the clock level, appear-
ing as about 3 pF when the clock is low, and about 5 pF
when the clock is high. This small change in capacitance can
be reasonably assumed to be a fixed capacitance. Care
should be taken to avoid driving the input beyond the supply
rails, even momentarily, as during power-up.
The CLC409 has been found to be a good device to drive the
ADC10221 because of its low voltage capability, wide band-
width, low distortion and minimal Differential Gain and Differ-
ential Phase. The CLC409 performs best with a feedback re-
sistor of about 100 ohms.
Care should be taken to keep digital noise out of the analog
input circuitry to maintain highest noise performance.
2.0 REFERENCE INPUTS
Note: Throughout this data sheet reference is made to
VREF+ and to VREF−. These refer to the internal voltage
across the reference ladder and are, nominally, VREF+ S and
VREF− S, respectively.
Figure 4 shows a simple reference biasing scheme with
minimal components. While this circuit might suffice for
some applications, it does suffer from thermal drift because
the external 750Ω resistor at pins 1 and 2 will have a differ-
ent temperature coefficient than the on-chip resistors. Also,
the on-chip resistors, while well matched to each other, will
have a large tolerance compared with any external resistors,
causing the value of VREF- to be quite variable.
The circuit of Figure 5 is an improvement over the circuit of
Figure 4 in that both ends of the reference ladder are defined
with reference voltages. This reduces problems of high refer-
ence variability and thermal drift, but requires two reference
sources.
In addition to the usual VREF+ and VREF− reference inputs,
the ADC10221 has two sense outputs for precision control of
the ladder voltages. These sense outputs (VREF+ S and
VREF− S) compensate for errors due to IR drops between the
source of the reference voltages and the ends of the refer-
ence ladder itself.
With the addition of two op-amps, the voltages at the top and
bottom of the reference ladder can be forced to the exact
value desired, as shown in Figure 6.
DS101038-18
FIGURE 4. Simple, low component cournt reference biasing
11 www.national.com
11 Page | ||
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| PDF Descargar | [ Datasheet ADC10221CIVT.PDF ] | |
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