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ADC10221 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC10221
Beschreibung 10-Bit/ 15 MSPS/ 98 mW A/D Converter with Internal Sample and Hold
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 16 Seiten
ADC10221 Datasheet, Funktion
January 2000
ADC10221
10-Bit, 15 MSPS, 98 mW A/D Converter with Internal
Sample and Hold
General Description
The ADC10221 is the first in a family of low power, high per-
formance CMOS analog-to-digital converters. It can digitize
signals to 10 bits resolution at sampling rates up to 20 MSPS
(15 MSPS guaranteed) while consuming a typical 98 mW
from a single 5V supply. Reference force and sense pins al-
low the user to connect an external reference buffer amplifier
to ensure optimal accuracy. The ADC10221 is guaranteed to
have no missing codes over the full operating temperature
range. The unique two stage architecture achieves 9.2 Effec-
tive Bits with a 10MHz input signal and a 20MHz clock fre-
quency. Output formatting is straight binary coding.
To ease interfacing to 3V systems, the digital I/O power pins
of the ADC10221 can be tied to a 3V power source, making
the outputs 3V compatible. When not converting, power con-
sumption can be reduced by pulling the PD (Power Down)
pin high, placing the converter into a low power standby
state, where it typically consumes less than 4 mW. The
ADC10221’s speed, resolution and single supply operation
make it well suited for a variety of applications in video, im-
aging, communications, multimedia and high speed data ac-
quisition. Low power, single supply operation ideally suit the
ADC10221 for high speed portable applications, and its
speed and resolution are ideal for charge coupled device
(CCD) input systems.
The ADC10221 comes in a space saving 32-pin TQFP and
operates over the industrial (−40˚C TA +85˚C) tempera-
ture range.
Features
n Internal Sample-and-Hold
n Single +5V Operation
n Low Power Standby Mode
n Guaranteed No Missing Codes
n TTL/CMOS or 3V Logic Input/Output Compatible
Key Specifications
n Resolution
n Conversion Rate
n ENOB 10 MHz Input,
20 MHz Clock
n DNL
n Power Consumption
n Low Power Standby Mode
10 Bits
20 MSPS (typ)
15 MSPS (min)
9.2 Bits (typ)
0.35 LSB (typ)
98 mW (typ)
<4 mW (typ)
Applications
n Digital Video
n Document Scanners
n Medical Imaging
n Electro-Optics
n Plain Paper Copiers
n CCD Imaging
Connection Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101038
DS101038-1
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ADC10221 Datasheet, Funktion
Converter Electrical Characteristics (Continued)
The following specifications
CL = 20pF, fCLK = 15 MHz,
apply
RS =
for VA = +5.0VDC, VD
25. Boldface limits
= 5.0VDC,
apply for
VD
TA
=I/OTM=IN5t.o0VTDMCA,XV:RaEllF+oth=e+r 3li.m5VitsDCT,AV=RE2F5−˚C=(N+o1t.e5V7D) C,
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
Reference and Analog Input Characteristics
RREF
Reference Ladder
Resistance
1000
850
1150
(min)
(max)
VREF+
VREF
Positive Reference Voltage
Negative Reference
Voltage
3.5 4.0 V(max)
1.5 1.3 V(min)
(VREF+) − Total Reference Voltage
(VREF −)
2.0 1.0 V(min)
2.7 V(max)
DC and Logic Electrical Characteristics
The following specifications apply
CL = 20 pF, fCLK = 15 MHz, RS =
for VA
25.
= +5.0VDC, VD
Boldface limits
=ap+p5l.y0VfoDrC,TVAD=I/TOM=IN
5.0VDC, VREF+ = +3.5VDC,
to TMAX: all other limits TA
V=R2EF5−˚C=(N+1o.t5eV7D)C,
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
CLK, OE, PD, Digital Input Characteristics
VIH Logical 1Input Voltage VD = 5.5V
VIL Logical 0Input Voltage VD = 4.5V
IIH Logical 1Input Current VIH = VD
IIL Logical 0Input Current VIL = DGND
D00 - D13 Digital Output Characteristics
2.0 V(min)
1.0 V(max)
10 µA
−10 µA
VOH
Logical 1Output
Voltage
VOL
Logical 0Output
Voltage
TRI-STATE Output
IOZ Current
IOS Output Short Circuit
Current
Power Supply Characteristics
VD I/O = + 4.5V, IOUT = −0.5 mA
VD I/O = + 2.7V, IOUT = −0.5 mA
VD I/O = + 4.5V, IOUT = 1.6 mA
VD I/O = + 2.7V, IOUT = 1.6 mA
VOUT = DGND
VOUT = VD
VD I/O = 3V
VD I/O = 5V
4.0 V(min)
2.4 V(min)
0.4 V(max)
0.4 V(max)
−10 µA
10 µA
±12 mA
±25 mA
IA
Analog Supply Current
PD = LOW, Ref not included
PD = HIGH, Ref not included
14.5
0.5
16 mA(max)
ID +
IDI/O
PD
Digital Supply Current
Power Consumption
PD = LOW, Ref not included
PD = HIGH, Ref not included
5
0.2
6 mA(max)
98 110 mW (max)
AC Electrical Characteristics
Tt=rch2e=5f˚toCfcll(oN=wo5itnegn7ss,)pReScif=ica2t5ion.sCaLp(pdlyatfaorbVusA
l=oa+d5in.0gV) D=C2, 0VDpFI/,OB=old5.f0aVceDCl,imViRtsEFa+p=ply+3f.o5rVTDAC,=VTREMFIN
=
to
+1.5VDC,
TMAX: all
fCLK = 15 MHz,
other limits TA
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
fCLK1
fCLK2
tCH
tCL
Maximum Clock Frequency
Minimum Clock Frequency
Clock High Time
Clock Low Time
Duty Cycle
20 15 MHz(min)
1 MHz(max)
23 ns(min
23 ns(min)
50
45 %(min)
55 %(max)
Pipeliine Delay (Latency)
2.0 Clock Cycles
trc, tfc
Clock Input Rise and Fall Time
5 ns(max)
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ADC10221 pdf, datenblatt
Applications Information (Continued)
DS101038-19
FIGURE 5. Better low component count reference biasing
The VREF+ F and VREF− F pins should each be bypassed to
AGND with 10 µF tantalum or electrolytic and 0.1 µF ceramic
capacitors. The circuit of Figure 6 may be used if it is desired
to obtain precise reference voltages. The LMC6082 in this
circuit was chosen for its low offset voltage, low voltage ca-
pability and low cost.
Since the current flowing through the sense lines (those lines
associated with VREF+ S and VREF− S) is essentially zero,
there is negligible voltage drop across any resistance in se-
ries with these sense pins and the voltage at the inverting in-
put of the op-amp accurately represents the voltage at the
top (or bottom) of the ladder. The op-amp drives the force in-
put, forcing the voltage at the ends of the ladder to equal the
voltage at the op-amp’s non-inverting input, plus any offset
voltage. For this reason, op-amps with low VOS, such as the
LMC6081 and LMC6082, should be used for this application.
Voltages at the reference sense pins (VREF+ S and VREF− S)
should be within the range specified in the Operating Ratings
table (2.3V to 4.0V for VREF+ and 1.3V to 3.0V for VREF−).
Any device used to drive the reference pins should be able to
source sufficient current into the VREF+ F pin and sink suffi-
cient current from the VREF− F pin when the ladder is at its
minimum value of 850 Ohms.
The reference voltage at the top of the ladder (VREF+) may
take on values as low as 1.0V above the voltage at the bot-
tom of the ladder (VREF−) and as high as (VA - 1.0V) Volts.
The voltage at the bottom of the ladder (VREF−) may take on
values as low as 1.3 Volts and as high as 3.0V. However, to
minimize noise effects and ensure accurate conversions, the
total reference voltage range (VREF+ - VREF−) should be a
minimum of 2.0V and a maximum of 2.7V.
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