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ADC10158 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC10158
Beschreibung 10-Bit Plus Sign 4 s ADCs with 4- or 8-Channel MUX/ Track/Hold and Reference
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 23 Seiten
ADC10158 Datasheet, Funktion
November 1999
ADC10154/ADC10158
10-Bit Plus Sign 4 µs ADCs with 4- or 8-Channel MUX,
Track/Hold and Reference
General Description
The ADC10154 and ADC10158 are CMOS 10-bit plus sign
successive approximation A/D converters with versatile ana-
log input multiplexers, track/hold function and a 2.5V
band-gap reference. The 4-channel or 8-channel multiplex-
ers can be software configured for single-ended, differential
or pseudo-differential modes of operation.
The input track/hold is implemented using a capacitive array
and sampled-data comparator.
Resolution can be programmed to be 8-bit, 8-bit plus sign,
10-bit or 10-bit plus sign. Lower-resolution conversions can
be performed faster.
The variable resolution output data word is read in two bytes,
and can be formatted left justified or right justified, high byte
first.
Applications
n Process control
n Instrumentation
n Test equipment
Features
n 4- or 8- channel configurable multiplexer
n Analog input track/hold function
n 0V to 5V analog input range with single +5V power
supply
n −5V to +5V analog input voltage range with ±5V
supplies
n Fully tested in unipolar (single +5V supply) and bipolar
(dual ±5V supplies) operation
n Programmable resolution/speed and output data format
n Ratiometric or Absolute voltage reference operation
n No zero or full scale adjustment required
n No missing codes over temperature
n Easy microprocessor interface
Key Specifications
n Resolution
n Integral linearity error
n Unipolar power dissipation
n Conversion time (10-bit + sign)
n Conversion time (8-bit)
n Sampling rate (10-bit + sign)
n Sampling rate (8-bit)
n Band-gap reference
10-bit plus sign
±1 LSB (max)
33 mW (max)
4.4 µs (max)
3.2 µs (max)
166 kHz
207 kHz
2.5V ±2.0% (max)
ADC10158 Simplified Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011225
DS011225-1
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ADC10158 Datasheet, Funktion
Electrical Characteristics
The following specifications
operation or V= −5.0 VDC
apply for V+ = AV+ = DV+ = +
for bipolar operation, and fCLK
=5.05.0VDMCH, zVRuEnFle+s=s
5.000 VDC, VREF− =
otherwise specified.
GND, V
Boldface
= GND for unipolar
limits apply for TA
= TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Note 16)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limit)
AC CHARACTERISTICS
fCLK Clock Frequency
8 5.0 MHz (Max)
10 kHz (Min)
Clock Duty Cycle
20 % (Min)
80 % (Max)
tC
Conversion
8-Bit Unipolar Mode
Time
fCLK = 5.0 MHz
8-Bit Bipolar Mode
fCLK = 5.0 MHz
10-Bit Unipolar Mode
fCLK = 5.0 MHz
10-Bit Bipolar Mode
fCLK = 5.0 MHz
tA Acquisition Time
fCLK = 5.0 MHz
tCR Delay between Falling Edge of
CS and Falling Edge of RD
16 1/fCLK
3.2 µs (Max)
18 1/fCLK
3.6 µs (Max)
20 1/fCLK
4.0 µs (Max)
22 1/fCLK
4.4 µs (Max)
6 1/fCLK
1.2 µs
0 5 ns (Min)
tRC Delay betwee Rising Edge
RD and Rising Edge of CS
0 5 ns (Min)
tCW Delay between Falling Edge
of CS and Falling Edge of WR
0 5 ns (Min)
tWC Delay between Rising Edge
of WR and Rising Edge of CS
0 5 ns (Min)
tRW Delay between Falling Edge
of RD and Falling Edge of WR
0 5 ns (Min)
tW(WR)
tWS
tDS
tDH
tWR
WR Pulse Width
WR High to CLK÷2 Low Set-Up Time
Data Set-Up Time
Data Hold Time
Delay from Rising Edge
of WR to Rising Edge RD
25 50 ns (Min)
5 ns (Max)
6 15 ns (Max)
0 5 ns (Max)
0 5 ns (Min)
tACC
Access Time (Delay from Falling
Edge of RD to Output Data Valid)
CL = 100 pF
25 45 ns (Max)
tWI, tRI
Delay from Falling Edge
of WR or RD to Reset of INT
CL = 100 pF
25 40 ns (Max)
tINTL
Delay from Falling Edge of CLK÷2 to
Falling Edge of INT
40 ns
t1H, t0H
TRI-STATE Control (Delay from
Rising Edge of RD to Hi-Z State)
CL = 10 pF, RL = 1 k
20
35 ns (Max)
tRR Delay between Successive
RD Pulses
25 50 ns (Min)
tP Delay between Last Rising Edge
of RD and the Next Falling
20 50 ns (Min)
Edge of WR
CIN
COUT
Capacitance of Logic Inputs
Capacitance of Logic Outputs
5 pF
5 pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
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6

6 Page









ADC10158 pdf, datenblatt
Timing Diagrams (Continued)
DS011225-16
DIAGRAM 2. Starting a Conversion without Changing the MUX Channel or Output Configuration
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DIAGRAM 3. Reading the Conversion Result
12
DS011225-17

12 Page





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