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ADC10061 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC10061
Beschreibung 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 14 Seiten
ADC10061 Datasheet, Funktion
June 1999
ADC10061/ADC10062/ADC10064
10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
General Description
Using an innovative, patented multistep* conversion tech-
nique, the 10-bit ADC10061, ADC10062, and ADC10064
CMOS analog-to-digital converters offer sub-microsecond
conversion times yet dissipate a maximum of only 235 mW.
The ADC10061, ADC10062, and ADC10064 perform a
10-bit conversion in two lower-resolution “flashes”, thus
yielding a fast A/D without the cost, power dissipation, and
other problems associated with true flash approaches. The
ADC10061 is pin-compatible with the ADC1061 but much
faster, thus providing a convenient upgrade path for the
ADC1061.
The analog input voltage to the ADC10061, ADC10062, and
ADC10064 is sampled and held by an internal sampling cir-
cuit. Input signals at frequencies from dc to over 200 kHz
can therefore be digitized accurately without the need for an
external sample-and-hold circuit.
The ADC10062 and ADC10064 include a “speed-up” pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 350 ns with
only a small increase in linearity error.
For ease of interface to microprocessors, the ADC10061,
ADC10062, and ADC10064 have been designed to appear
as a memory location or I/O port without the need for exter-
nal interface logic.
*U.S. Patent Number 4918449
Features
n Built-in sample-and-hold
n Single +5V supply
n 1, 2, or 4-input multiplexer options
n No external clock required
n Speed adjust pin for faster conversions (ADC10062
and ADC10064). See ADC10662/4 for high speed
guaranteed performance.
Key Specifications
n Conversion time to 10 bits
600 ns typical,
n 900 ns max over temperature
n Sampling Rate
800 kHz
n Low power dissipation
235 mW (max)
n Total unadjusted error
±1.0 LSB (max)
n No missing codes over temperature
Applications
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
Simplified Block Diagram
*ADC10061 Only
**ADC10062 and ADC10064 Only
***ADC10064 Only
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011020
DS011020-1
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ADC10061 Datasheet, Funktion
AC Electrical Characteristics (Continued)
Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if tSH is shorter than the value specified. See curves of Accuracy vs tSH.
Typical Performance Characteristics
Zero (Offset) Error
vs Reference Voltage
Linearity Error
vs Reference Voltage
Analog Supply Current
vs Temperature
DS011020-16
Digital Supply Current
vs Temperature
Conversion Time
vs Temperature
DS011020-17
Conversion Time
vs Temperature
DS011020-18
DS011020-19
Conversion Time
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)
DS011020-20
Conversion Time
vs Speed-Up Resistor
(ADC10062 and ADC10064 Only)
Spectral Response
with100 kHz Sine
Wave Input
DS011020-21
DS011020-22
DS011020-23
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ADC10061 pdf, datenblatt
Applications Information (Continued)
digitize AC signals without significant spectral errors and
without adding noise to the digitized signal. Dynamic charac-
teristics such as signal-to-noise ratio (SNR) and total har-
monic distortion (THD), are quantitative measures of this ca-
pability.
An A/D converter’s AC performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal wave-
form is applied to the A/D converter’s input, and the trans-
form is then performed on the digitized waveform. The re-
sulting spectral plot might look like the ones shown in the
typical performance curves. The large peak is the fundamen-
tal frequency, and the noise and distortion components (if
any are present) are visible above and below the fundamen-
tal frequency. Harmonic distortion components appear at
whole multiples of the input frequency. Their amplitudes are
combined as the square root of the sum of the squares and
compared to the fundamental amplitude to yield the THD
specification. Typical values for THD are given in the table of
Electrical Characteristics.
Signal-to-noise ratio is the ratio of the amplitude at the fun-
damental frequency to the rms value at all other frequencies,
excluding any harmonic distortion components. Typical val-
ues are given in the Electrical Characteristics table. An alter-
native definition of signal-to-noise ratio includes the distor-
tion components along with the random noise to yield a
signal-to-noise-plus-distortion ratio, or S/(N + D).
The THD and noise performance of the A/D converter will
change with the frequency of the input signal, with more dis-
tortion and noise occurring at higher signal frequencies. One
way of describing the A/D’s performance as a function of sig-
nal frequency is to make a plot of “effective bits” versus fre-
quency. An ideal A/D converter with no linearity errors or
self-generated noise will have a signal-to-noise ratio equal to
(6.02n + 1.76) dB, where n is the resolution in bits of the A/D
converter. A real A/D converter will have some amount of
noise and distortion, and the effective bits can be found by:
where S/(N + D) is the ratio of signal to noise and distortion,
which can vary with frequency.
As an example, an ADC10061 with a 5 VP-P, 100 kHz sine
wave input signal will typically have a
signal-to-noise-plus-distortion ratio of 59.2 dB, which is
equivalent to 9.54 effective bits. As the input frequency in-
creases, noise and distortion gradually increase, yielding a
plot of effective bits or S/(N + D) as shown in the typical per-
formance curves.
8.0 SPEED ADJUST
In applications that require faster conversion times, the
Speed Adjust pin (pin 14 on the ADC10062, pin 17 on the
ADC10064) can significantly reduce the conversion time.
The speed adjust pin is connected to an on-chip current
source that determines the converter’s internal timing. By
connecting a resistor between the speed adjust pin and
ground as shown in Figure 4, the internal programming cur-
rent is increased, which reduces the conversion time. As an
example, an 18k resistor reduces the conversion time of a
typical part from 600 ns to 350 ns with no significant effect on
linearity. Using smaller resistors to further decrease the con-
version time is possible as well, although the linearity will be-
gin to degrade somewhat (see curves). Note that the resistor
value needed to obtain a given conversion time will vary from
part to part, so this technique will generally require some
“tweaking” to obtain satisfactory results.
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