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ADC10040 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC10040
Beschreibung 10-Bit/ 40 MSPS/ 3V/ 55.5 mW A/D Converter
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 19 Seiten
ADC10040 Datasheet, Funktion
November 2004
ADC10040
10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter
General Description
The ADC10040 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 10-bit
digital words at 40 Megasamples per second (MSPS). This
converter uses a differential, pipeline architecture with digital
error correction and an on-chip sample-and-hold circuit to
provide a complete conversion solution, and to minimize
power consumption, while providing excellent dynamic per-
formance. A unique sample-and-hold stage yields a full-
power bandwidth of 400 MHz. Operating on a single 3.0V
power supply, this device consumes just 55.5 mW at
40 MSPS, including the reference current. The Standby
feature reduces power consumption to just 13.5 mW.
The differential inputs provide a full scale selectable input
swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a
single-ended input. Full use of the differential input is recom-
mended for optimum performance. An internal +1.2V preci-
sion bandgap reference is used to set the ADC full-scale
range, and also allows the user to supply a buffered refer-
enced voltage for those applications requiring increased ac-
curacy. The output data format is 10-bit offset binary, or two’s
complement.
This device is available in the 28-lead TSSOP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
Features
n Single +3.0V operation
n Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input
swing
n 400 MHz −3 dB input bandwidth
n Low power consumption
n Standby mode
n On-chip reference and sample-and-hold amplifier
n Offset binary or two’s complement data format
n Separate adjustable output driver supply to
accommodate 2.5V and 3.3V logic families
n 28-pin TSSOP package
Key Specifications
n Resolution
n Conversion Rate
n Full Power Bandwidth
n DNL
n SNR (fIN = 11 MHz)
n SFDR (fIN = 11 MHz)
n Data Latency
n Supply Voltage
n Power Consumption, 40 MHz
10 Bits
40 MSPS
400 MHz
±0.3 LSB (typ)
59.6 dB (typ)
−80 dB (typ)
6 Clock Cycles
+3.0V
55.5 mW
Applications
n Ultrasound and Imaging
n Instrumentation
n Cellular Based Stations/Communications Receivers
n Sonar/Radar
n xDSL
n Wireless Local Loops
n Data Acquisition Systems
n DSP Front Ends
Connection Diagram
© 2004 National Semiconductor Corporation DS200778
20077801
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ADC10040 Datasheet, Funktion
DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications
apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.20V, (Externally Supplied)
fCLK = 40 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C
Symbol
Parameter
CLK, DF, STBY, SENSE
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
D0–D9 OUTPUT CHARACTERISTICS
Logical “1” Output Voltage
Logical “0” Output Voltage
DYNAMIC CONVERTER CHARACTERISTICS
ENOB
Effective Number of Bits
SNR
Signal-to-Noise Ratio
SINAD
Signal-to-Noise Ratio + Distortion
2nd HD
2nd Harmonic
Conditions
IOUT = −0.5 mA
IOUT = 1.6 mA
fIN = 11 MHz
fIN = 19 MHz
fIN = 11 MHz
fIN = 19 MHz
fIN = 11 MHz
fIN = 19 MHz
fIN = 11 MHz
fIN = 19 MHz
3rd HD
3rd Harmonic
fIN = 11 MHz
fIN = 19 MHz
THD
Total Harmonic Distortion (First 6
Harmonics)
fIN = 11 MHz
f.IN = 19 MHz
SFDR
Spurious Free Dynamic Range
(Excluding 2nd and 3rd Harmonic)
fIN = 11 MHz
fIN = 19 MHz
Min Typ Max
2
0.8
+10
−10
VDDIO−0.2
0.4
9.4, 9.3
9.4, 9.3
58.7, 58.1
58.6, 58
58.6, 58
58.5, 57.8
−75.9,
−74.7
−74.4,
−73
−69.5,
−67.5
−68.8,
−66.7
−69.5,
−67.5
−68.8,
−66.7
−75.8,
−74.5
−75.7,
−74.3
9.6
9.6
59.6
59.5
59.5
59.4
−89
−86
−78
−77
−78
−77
−80
−80
Units
V
V
µA
µA
V
V
Bits
Bits
dB
dB
dB
dB
dBc
dBc
dBc
dBc
dB
dB
dBc
dBc
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ADC10040 pdf, datenblatt
Typical Performance Characteristics Unless otherwise specified, the following specifications apply:
VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P, STBY = 0V, VREF = 1.2V, (External Supply) fCLK = 40 MHz,
fIN = 19 MHz, 50% Duty Cycle. (Continued)
SNR vs. Temperature
THD vs. VDDA
THD vs. VDDIO
20077824
THD vs. fCLK
20077825
SNR vs. IRS
20077826
THD vs. IRS
20077827
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