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PDF ADC10030CIVT Data sheet ( Hoja de datos )
| Número de pieza | ADC10030CIVT | |
| Descripción | 10-Bit/ 30 MSPS/ 125 mW A/D Converter with Internal Sample and Hold | |
| Fabricantes | National Semiconductor | |
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January 2000
ADC10030
10-Bit, 30 MSPS, 125 mW A/D Converter with Internal
Sample and Hold
General Description
The ADC10030 is a low power, high performance CMOS
analog-to-digital converter that digitizes signals to 10 bits
resolution at sampling rates up to 30 Msps while consuming
a typical 125 mW from a single 5V supply. Reference force
and sense pins allow the user to connect an external refer-
ence buffer amplifier to ensure optimal accuracy. No missing
codes is guaranteed over the full operating temperature
range. The unique two-stage architecture achieves 9.1 Ef-
fective Bits with a 15 MHz input signal and a 30 MHz clock
frequency. Output formatting is straight binary coding.
To ease interfacing to 3V systems, the digital I/O power pins
of the ADC10030 can be tied to a 3V power source, making
the outputs 3V compatible. When not converting, power con-
sumption can be reduced by pulling the PD (Power Down)
pin high, placing the converter into a low power standby
state, where it typically consumes less than 4 mW. The
ADC10030’s speed, resolution and single supply operation
makes it well suited for a variety of applications in video, im-
aging, communications, multimedia and high speed data ac-
quisition. Low power, single supply operation ideally suit the
ADC10030 for high speed portable applications, and its
speed and resolution are ideal for charge coupled device
(CCD) input systems.
The ADC10030 comes in a space saving 32-pin TQFP and
operates over the industrial (−40˚C ≤ TA ≤ +85˚C) tempera-
ture range.
Features
n Internal Sample-and-Hold
n Single +5V Operation
n Low Power Standby Mode
n Guaranteed No Missing Codes
n TRI-STATE® Outputs
n TTL/CMOS or 3V Logic Input/Output Compatible
Key Specifications
n Resolution
n Conversion Rate
n ENOB @ 15 MHz Input
n DNL
n Conversion Latency
n PSRR
n Power Consumption
n Low Power Standby Mode
10 Bits
30 Msps
9.1 Bits (typ)
0.40 LSB (typ)
2 Clock Cycles
56 dB
125 mW (typ)
<3.5 mW (typ)
Applications
n Digital Video
n Communications
n Document Scanners
n Medical Imaging
n Electro-Optics
n Plain Paper Copiers
n CCD Imaging
Connection Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101064
DS101064-1
www.national.com
1 page  
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage (V = VA = VD)
6.5V
Voltage on Any Pin
−0.3V to (VA or VD +0.3V)
Input Current at Any Pin (Note 3)
±25 mA
Package Input Current (Note 3)
±50 mA
Package Dissipation at TA = 25˚C
ESD Susceptibility (Note 5)
See (Note 4)
Human Body Model
1500V
Machine Model
200V
Soldering Temp., Infrared, 10 sec. (Note 6)
300˚C
Storage Temperature
−65˚C to +150˚C
Operating Ratings (Notes 1, 2)
Operating Temperature Range
VA, VD Supply Voltage
VD I/O Supply Voltage
VIN Voltage Range
VREF+ Voltage Range
VREF− Voltage Range
PD, CLK, OE Voltage Range
−40˚C ≤ TA ≤ +85˚C
+4.75V to +5.5V
+2.7V to 5.5V
1.7V to (VA−1.2V)
2.6V to (VA−1.2V)
1.7V to 2.8V
−0.3V to +5.5V
Converter Electrical Characteristics
The following specifications apply
CL = 20 pF, fCLK = 27 MHz, RS =
for VA
50Ω.
= +5.0VDC, VD
Boldface limits
= 5.0VDC,
apply for
VD
TA
I=/OTM=IN+5to.0VTDMCA,XV: RalElFo+th=er+l3im.5itVsDTCA,
V=R2E5F−˚C=(N+o1t.e757V)DC,
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
Static Converter Characteristics
INL Integral Non-Linearity
±0.45
±1.0
LSB(max)
DNL
Differential-Non-Linearity
±0.40
±0.95
LSB(max)
Resolution with No Missing
Codes
10 Bits
Zero Scale Offset Error
−4 mV
Full-Scale Offset Error
+3 mV
Dynamic Converter Characteristics
ENOB
Effective Number of Bits
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
SNR
Signal-to-Noise Ratio
THD
Total Harmonic Distortion
SFDR
Spurious Free Dynamic
Range
Overrange Output Code
fIN = 1.0 MHz
fIN = 4.43 MHz
fIN = 13.5 MHz
fIN = 4.43 MHz, fCLK = 30 MHz
fIN = 15.0 MHz, fCLK = 30 MHz
fIN = 1.0 MHz
fIN = 4.43 MHz
fIN = 13.5 MHz
fIN = 4.43 MHz, fCLK = 30 MHz
fIN = 15.0 MHz, fCLK = 30 MHz
fIN = 1.0 MHz
fIN = 4.43 MHz
fIN = 13.5 MHz
fIN = 4.43 MHz, fCLK = 30 MHz
fIN = 15.0 MHz, fCLK = 30 MHz
fIN = 1.0 MHz
fIN = 4.43 MHz
fIN = 13.5 MHz
fIN = 4.43 MHz, fCLK = 30 MHz
fIN = 15.0 MHz, fCLK = 30 MHz
fIN = 1.0 MHz
fIN = 4.43 MHz
fIN = 13.5 MHz
fIN = 4.43 MHz, fCLK = 30 MHz
fIN = 15.0 MHz, fCLK = 30 MHz
VIN > VREF+
9.6
9.4
9.4 8.6
9.3
9.1
60
59
58 53.5
58
57
60
59
59 54
59
58
−72
−69
−66 −61
−64
−61
73
71
68
66
62
1023
Bits
Bits
Bits
Bits
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
5 www.national.com
5 Page 
Timing Diagram (Continued)
DS101064-17
FIGURE 2. AC Test Circuit
Functional Description
The ADC10030 maintains excellent dynamic performance
for input signals up to and exceeding half the clock fre-
quency. The use of an internal sample-and-hold amplifier
(SHA) enables sustained dynamic performance for signals of
input frequency beyond the clock rate, lowers the converter’s
input capacitance and reduces the number of external com-
ponents required.
The analog signal at VIN that is within the voltage range set
by VREF+ S and VREF− S are digitized to ten bits at up to
30 MSPS. Input voltages below VREF− S will cause the out-
put word to consist of all zeroes. Input voltages above
VREF+ S will cause the output word to consist of all ones.
VREF+ S has a range of 2.6V to 3.8V, while VREF− S has a
range of 1.7V to 2.8V. VREF+ S should always be at least
1.0V more positive than VREF− S.
Data is acquired at the falling edge of the clock and the digi-
tal equivalent of that data is available at the digital outputs
2.0 clock cycles plus tOD later. The ADC10030 will convert as
long as the clock signal is present at pin 9 and the PD pin is
low. The Output Enable pin (OE), when low, enables the out-
put pins. The digital outputs are in the high impedance state
when the OE pin or the PD pin is high.
Applications Information
1.0 THE ANALOG INPUT
The analog input of the ADC10030 is a switch (transmission
gate) followed by a switched capacitor amplifier. The capaci-
tance seen at the input changes with the clock level, appear-
ing as about 3 pF when the clock is low, and about 5 pF
when the clock is high. This small change in capacitance can
be reasonably assumed to be a fixed capacitance. Care
should be taken to avoid driving the input beyond the supply
rails, even momentarily, as during power-up.
The CLC409 has been found to be a good device to drive the
ADC10030 because of its wide bandwidth, low distortion and
DS101064-16
FIGURE 3. tEN, tDIS Test Circuit
minimal Differential Gain and Differential Phase. The
CLC409 performs best with a feedback resistor of about
100Ω.
Care should be taken to keep digital noise out of the analog
input circuitry to maintain highest noise performance.
2.0 REFERENCE INPUTS
Note: Throughout this data sheet reference is made to VREF+ and to VREF−.
These refer to the internal voltage across the reference ladder and are,
nominally, VREF+ S and VREF− S, respectively.
Figure 4 shows a simple reference biasing scheme with
minimal components. While this circuit might suffice for
some applications, it does suffer from thermal drift because
the external will have a different temperature coefficient than
the on-chip resistors. Also, the on-chip resistors, while well
matched to each other, will have a large tolerance compared
with any external resistors, causing the value of VREF+ and
VREF− to be somewhat variable.
The VREF+ F and VREF− F pins should each be bypassed to
AGND with 10 µF tantalum or electrolytic capacitors and
0.1 µF ceramic capacitors.
The circuit of Figure 5 is an improvement over the circuit of
Figure 4 in that the positive end of the reference ladder is de-
fined with a reference voltage. This reduces problems of
high reference variability and thermal drift.
In addition to the usual VREF+F and VREF−F reference in-
puts, the ADC10030 has two sense outputs for precision
control of the ladder voltages. These sense outputs (VREF+
S and VREF− S) compensate for errors due to IR drops be-
tween the source of the reference voltages and the ends of
the reference ladder itself.
With the addition of two op-amps, the voltages at the top and
bottom of the reference ladder can be forced to the exact
value desired, as shown in Figure 6.
11 www.national.com
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADC10030CIVT.PDF ] | |
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