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ADC08D1000 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC08D1000
Beschreibung High Performance/ Low Power/ Dual 8-Bit/ 1 GSPS A/D Converter
Hersteller National Semiconductor
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Gesamt 30 Seiten
ADC08D1000 Datasheet, Funktion
ADVANCE INFORMATION
September 2004
ADC08D1000
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D
Converter
General Description
NOTE: This product is currently in development. – ALL
specifications are design targets and are subject to
change.
The ADC08D1000 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 1.6 GSPS. Consuming
a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and
interpolating architecture, the fully differential comparator
design, the innovative design of the internal sample-and-
hold amplifier and the self-calibration scheme enable a very
flat response of all dynamic parameters beyond Nyquist,
producing a high 7.5 ENOB with a 500 MHz input signal and
a 1 GHz sample rate while providing a 10-18 B.E.R. Output
formatting is offset binary and the LVDS digital outputs are
compliant with IEEE 1596.3-1996, with the exception of a
reduced common mode voltage of 0.8V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved
and used as a single 2 GSPS ADC.
The converter typically consumes less than 20 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the indus-
trial (-40˚C TA +85˚C) temperature range.
Features
n Internal Sample-and-Hold
n Single +1.9V ±0.1V Operation
n Choice of SDR or DDR output clocking
n Interleave Mode for 2x Sampling Rate
n Multiple ADC Synchronization Capability
n Guaranteed No Missing Codes
n Serial Interface for Extended Control
n Fine Adjustment of Input Full-Scale Range and Offset
Key Specifications
n Resolution
n Max Conversion Rate
n Bit Error Rate
n ENOB @ 500 MHz Input
n DNL
n Power Consumption
— Operating
— Power Down Mode
8 Bits
1 GSPS (min)
10-18 (typ)
7.5 Bits (typ)
±0.25 LSB (typ)
1.6 W (typ)
20 mW (typ)
Applications
n Direct RF Down Conversion
n Digital Oscilloscopes
n Satellite Set-top boxes
n Communications Systems
n Test Instrumentation
Block Diagram
© 2004 National Semiconductor Corporation DS200974
20097453
www.national.com






ADC08D1000 Datasheet, Funktion
Pin Descriptions and Equivalent Circuits (Continued)
Pin Functions
Pin No.
Symbol
40, 51
,62, 73,
88, 99,
VDR
110, 121
1, 6, 9,
12, 21,
24, 27,
GND
41
42, 53,
64, 74,
87, 97,
DR GND
108, 119
52, 63,
98, 109,
NC
120
Equivalent Circuit
Description
Output Driver power supply pins. Bypass these pins to DR
GND.
Ground return for VA.
Ground return for VDR.
No Connection. Make no connection to these pins.
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ADC08D1000 pdf, datenblatt
Converter Electrical Characteristics (Continued)
Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Note 14: Each of the two converters of the ADC08D1000 has two LVDS output buses, which each clock data out at one half the sample rate. The data at each bus
is clocked out at one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one Input Clock cycle less than the latency of the first bus
(Dd0 through Dd7).
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