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PDF ADC0844CCN Data sheet ( Hoja de datos )
| Número de pieza | ADC0844CCN | |
| Descripción | 8-Bit uP Compatible A/D Converters with Multiplexer Options | |
| Fabricantes | National Semiconductor | |
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June 1999
ADC0844/ADC0848
8-Bit µP Compatible A/D Converters with Multiplexer
Options
General Description
The ADC0844 and ADC0848 are CMOS 8-bit successive ap-
proximation A/D converters with versatile analog input multi-
plexers. The 4-channel or 8-channel multiplexers can be
software configured for single-ended, differential or
pseudo-differential modes of operation.
The differential mode provides low frequency input common
mode rejection and allows offsetting the analog range of the
converter. In addition, the A/D’s reference can be adjusted
enabling the conversion of reduced analog ranges with 8-bit
resolution.
The A/Ds are designed to operate from the control bus of a
wide variety of microprocessors. TRI-STATE® output latches
that directly drive the data bus permit the A/Ds to be config-
ured as memory locations or I/O devices to the microproces-
sor with no interface logic necessary.
Features
n Easy interface to all microprocessors
n Operates ratiometrically or with 5 VDC
voltage reference
n No zero or full-scale adjust required
n 4-channel or 8-channel multiplexer with address logic
n Internal clock
n 0V to 5V input range with single 5V power supply
n 0.3" standard width 20-pin or 24-pin DIP
n 28 Pin Molded Chip Carrier Package
Key Specifications
n Resolution
n Total Unadjusted Error
n Single Supply
n Low Power
n Conversion Time
8 Bits
±1⁄2 LSB and ± 1 LSB
5 VDC
15 mW
40 µs
Block and Connection Diagrams
*ADC0848 shown in DIP Package CH5-CH8 not included on the ADC0844
TRI-STATE® is a registered trademark of National Semiconductor Corp.
© 1999 National Semiconductor Corporation DS005016
DS005016-1
www.national.com
1 page  
Typical Performance Characteristics
Logic Input Threshold
Voltage vs Supply Voltage
Output Current vs
Temperature
Power Supply Current vs
Temperature
DS005016-31
Linearity Error vs VREF
DS005016-32
Conversion Time vs VSUPPLY
DS005016-33
Conversion Time vs
Temperature
DS005016-34
Unadjusted Offset Error vs
VREF Voltage
DS005016-35
DS005016-36
DS005016-37
5 www.national.com
5 Page 
Applications Information (Continued)
TABLE 2. ADC0848 MUX Addressing
MUX Address
CS WR RD
Channel
MUX
MA4 MA3 MA2 MA1 MA0
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 AGND
Mode
X L L L LL
H+ −
X L L L HL
H− +
X L L H LL
H
+−
X L L H H LLH
−+
Differential
X L H L LL
H
+−
X L H L HL
H
−+
X L HH LL
H
+−
X L H H HL
H
−+
L H L L LL
H+
−
L H L L HL H +
−
L H L H LL
H
+
−
L H L H H LLH
+
− Single-Ended
L HH L LL
H
+−
L H H L HL
H
+−
L HHH LL
H
+−
L H H H HL
H
+−
HH L L LL
H+
−
H H L L HL H +
−
HH L H LL
H
+
− Pseudo-
H H L H H LLH
+
− Differential
HHH L LL
H
+−
H H H L HL
H
+−
HHHH LL
H
+−
X X X X X LLL
Previous Channel Configuration
3.2 Input Current
Due to the sampling nature of the analog inputs, short dura-
tion spikes of current enter the “+” input and exit the “−” input
at the clock edges during the actual conversion. These cur-
rents decay rapidly and do not cause errors as the internal
comparator is strobed at the end of a clock period. Bypass
capacitors at the inputs will average these currents and
cause an effective DC current to flow through the output re-
sistance of the analog signal source. Bypass capacitors
should not be used if the source resistance is greater than
1 kΩ.
3.3 Input Source Resistance
The limitation of the input source resistance due to the DC
leakage currents of the input multiplexer is important. A
worst-case leakage current of ± 1 µA over temperature will
create a 1 mV input error with a 1 kΩ source resistance. An
op amp RC active low pass filter can provide both imped-
ance buffering and noise filtering should a high impedance
signal source be required.
4.0 OPTIONAL ADJUSTMENTS
4.1 Zero Error
The zero of the A/D does not require adjustment. If the mini-
mum analog input voltage value, VIN(MIN), is not ground, a
zero offset can be done. The converter can be made to out-
put 0000 0000 digital code for this minimum input voltage by
biasing any VIN (−) input at this VIN(MIN) value. This is useful
for either differential or pseudo-differential modes of input
channel configuration.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V− input and applying a small magnitude posi-
tive voltage to the V+ input. Zero error is the difference be-
tween actual DC input voltage which is necessary to just
cause an output digital code transition from 0000 0000 to
0000 0001 and the ideal 1⁄2 LSB value (1⁄2 LSB=9.8 mV for
VREF=5.000 VDC).
4.2 Full-Scale
The full-scale adjustment can be made by applying a differ-
ential input voltage which is 1 1⁄2 LSB down from the desired
analog full-scale voltage range and then adjusting the mag-
nitude of the VREF input for a digital output code changing
from 1111 1110 to 1111 1111.
4.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
should be properly adjusted first. A VIN (+) voltage which
equals this desired zero reference plus 1⁄2 LSB (where the
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