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ADC0844CCJ Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC0844CCJ
Beschreibung 8-Bit uP Compatible A/D Converters with Multiplexer Options
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 20 Seiten
ADC0844CCJ Datasheet, Funktion
June 1999
ADC0844/ADC0848
8-Bit µP Compatible A/D Converters with Multiplexer
Options
General Description
The ADC0844 and ADC0848 are CMOS 8-bit successive ap-
proximation A/D converters with versatile analog input multi-
plexers. The 4-channel or 8-channel multiplexers can be
software configured for single-ended, differential or
pseudo-differential modes of operation.
The differential mode provides low frequency input common
mode rejection and allows offsetting the analog range of the
converter. In addition, the A/D’s reference can be adjusted
enabling the conversion of reduced analog ranges with 8-bit
resolution.
The A/Ds are designed to operate from the control bus of a
wide variety of microprocessors. TRI-STATE® output latches
that directly drive the data bus permit the A/Ds to be config-
ured as memory locations or I/O devices to the microproces-
sor with no interface logic necessary.
Features
n Easy interface to all microprocessors
n Operates ratiometrically or with 5 VDC
voltage reference
n No zero or full-scale adjust required
n 4-channel or 8-channel multiplexer with address logic
n Internal clock
n 0V to 5V input range with single 5V power supply
n 0.3" standard width 20-pin or 24-pin DIP
n 28 Pin Molded Chip Carrier Package
Key Specifications
n Resolution
n Total Unadjusted Error
n Single Supply
n Low Power
n Conversion Time
8 Bits
±12 LSB and ± 1 LSB
5 VDC
15 mW
40 µs
Block and Connection Diagrams
*ADC0848 shown in DIP Package CH5-CH8 not included on the ADC0844
TRI-STATE® is a registered trademark of National Semiconductor Corp.
© 1999 National Semiconductor Corporation DS005016
DS005016-1
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ADC0844CCJ Datasheet, Funktion
TRI-STATE Test Circuits and Waveforms
t1H
t1H, CL = 10 pF
t0H
DS005016-4
tr = 20 ns
DS005016-5
t0H, CL = 10 pF
DS005016-6
Leakage Current Test Circuit
tr = 20 ns
DS005016-7
DS005016-8
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ADC0844CCJ pdf, datenblatt
Applications Information (Continued)
LSB is calculated for the desired analog span, 1 LSB = ana-
log span/256) is applied to selected “+” input and the zero
reference voltage at the corresponding “−” input should then
be adjusted to just obtain the 00HEX to 01HEX code transition.
a) Ratiometric
DS005016-16
DS005016-17
b) Absolute with a Reduced Span
FIGURE 2. Referencing Examples
The full-scale adjustment should be made [with the proper
VIN (−) voltage applied] by forcing a voltage to the VIN (+) in-
put which is given by:
The VREF (or VCC) voltage is then adjusted to provide a code
change from FEHEX to FFHEX. This completes the adjust-
ment procedure.
For an example see the Zero-Shift and Span Adjust circuit
below.
where VMAX=the high end of the analog input range and
VMIN=the low end (the offset zero) of the analog range. (Both
are ground referenced.)
Zero-Shift and Span Adjust (2VVIN5V)
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DS005016-18
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