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PDF ADC0833CCJ Data sheet ( Hoja de datos )
| Número de pieza | ADC0833CCJ | |
| Descripción | 8-Bit Serial I/O A/D Converter with 4-Channel Multiplexer | |
| Fabricantes | National Semiconductor | |
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December 1994
ADC0833 8-Bit Serial I O A D Converter
with 4-Channel Multiplexer
General Description
The ADC0833 series is an 8-bit successive approximation
A D converter with a serial I O and configurable input multi-
plexer with 4 channels The serial I O is configured to com-
ply with the NSC MICROWIRETM serial data exchange stan-
dard for easy interface to the COPSTM family of processors
as well as with standard shift registers or mPs
The 4-channel multiplexer is software configured for single-
ended or differential inputs when channel assigned by a 4-
bit serial word
The differential analog voltage input allows increasing the
common-mode rejection and offsetting the analog zero in-
put voltage value In addition the voltage reference input
can be adjusted to allow encoding any smaller analog volt-
age span to the full 8 bits of resolution
Key Specifications
Y Resolution
Y Total Unadjusted Error
Y Single Supply
Y Low Power
Y Conversion Time
g
8 Bits
LSB and g 1 LSB
5 VDC
23 mW
32 ms
Features
Y NSC MICROWIRE compatible – direct interface to COPS
family processors
Y Easy interface to all microprocessors or operates
‘‘stand alone’’
Y Works with 2 5V (LM336) voltage reference
Y No full-scale or zero adjust required
Y Differential analog voltage inputs
Y 4-channel analog multiplexer
Y Shunt regulator allows operation with high voltage
supplies
Y 0V to 5V input range with single 5V power supply
Y Remote operation with serial digital data link
Y TTL MOS input output compatible
Y 0 3 standard width 14-pin DIP package
Connection and Functional Diagrams
Dual-In-Line Package (J and N)
TL H 5607–14
Top View
Order Number ADC0833CCJ
ADC0833BCN or ADC0833CCN
See NS Package Number
J14A or N14A
COPSTM and MICROWIRETM are trademarks of National Semiconductor Corporation
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 5607
TL H 5607 – 1
RRD-B30M115 Printed in U S A
1 page  
AC Electrical Characteristics The following specifications apply for VCC e Va e 5V and tr e tf e 20 ns
unless otherwise specified These limits apply for TA e Tj e 25 C
Parameter
Conditions
Typ
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
fCLK Clock Frequency
Min
Max
10 kHz
400 kHz
TC Conversion Time
Clock Duty Cycle (Note 12) Min
Max
Not including MUX Addressing Time
8 1 fCLK
40 %
60 %
tSET-UP CS Falling Edge or
Data Input Valid to CLK
Rising Edge
250 ns
tHOLD Data Input Valid
after CLK Rising Edge
90 ns
tpd1 tpd0 CLK Falling
Edge to Output Data Valid
(Note 13)
CL e 100 pF
Data MSB First
Data LSB First
650
1500
ns
250 600 ns
t1H tOH Rising Edge of CS
to Data Output and SARS
Hi-Z
CL e 10 pF RL e 10k
CL e 100 pF RL e 2k
(see TRI-STATE Test Circuits)
125 250 ns
500 ns
CIN Capacitance of Logic
Input
5 pF
COUT Capacitance of Logic
Outputs
5 pF
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions
Note 2 All voltages are measured with respect to the ground pins
Note 3 Internal zener diodes (approx 7V) are connected from Va to GND and VCC to GND The zener at Va can operate as a shunt regulator and is connected to
VCC via a conventional diode Since the zener voltage equals the A D’s breakdown voltage the diode insures that VCC will be below breakdown when the device is
powered from Va Functionality is therefore guaranteed for Va operation even though the resultant voltage at VCC may exceed the specified Absolute Max of
6 5V It is recommended that a resistor be used to limit the max current into Va
Note 4 When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l Va) the absolute value of current at that pin should be limited
to 5 mA or less The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four
Note 5 Human body model 100 pF discharged through a 1 5 kX resistor
Note 6 Typicals are at 25 C and represent most likely parametric norm
Note 7 Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 8 Design limits are guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels
Note 9 See Applications section 3 0
Note 10 For VIN(b)tVIN(a) the digital output code will be 0000 0000 Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply Be careful during testing at low VCC levels (4 5V)
as high level analog inputs (5V) can cause this input diode to conduct especially at elevated temperatures and cause errors for analog inputs near full-scale The
spec allows 50 mV forward bias of either diode This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mV the
output code will be correct To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4 950 VDC over
temperature variations initial tolerance and loading
Note 11 Leakage current is measured with the clock not switching
Note 12 A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies In the case that an available clock has a duty cycle outside of
these limits the minimum time the clock is high or the minimum time the clock is low must be at least 1ms The maximum time the clock can be high is 60 ms The
clocked can be stopped when low so long as the analog input voltage remains stable
Note 13 Since data MSB first is the output of the comparator used in the successive approximation loop an additional delay is built in (see Block Diagram) to
allow for comparator response time
5
5 Page 
Functional Description (Continued)
4 When the start bit has been shifted into the start location
of the MUX register the input channel has been assigned
and a conversion is about to begin An interval of clock
period (where nothing happens) is automatically inserted to
allow the selected MUX channel to settle The SAR status
line goes high at this time to signal that a conversion is now
in progress and the DI line is disabled (it no longer accepts
data)
5 The data out (DO) line now comes out of TRI-STATE and
provides a leading zero for this one clock period of MUX
settling time
6 When the conversion begins the output of the SAR com-
parator which indicates whether the analog input is greater
than (high) or less than (low) each successive voltage from
the internal resistor ladder appears at the DO line on each
falling edge of the clock This data is the result of the con-
version being shifted out (with the MSB coming first) and
can be read by the processor immediately
7 After 8 clock periods the conversion is completed The
SAR status line returns low to indicate this clock cycle
later
8 If the programmer prefers the data can be read in an LSB
first format All 8 bits of the result are stored in an output
shift register The conversion result LSB first is automati-
cally shifted out the DO line after the MSB first data stream
The DO line then goes low and stays low until CS is re-
turned high
9 All internal registers are cleared when the CS line is high
If another conversion is desired CS must make a high to
low transition followed by address information
The DI and DO lines can be tied together and controlled
through a bidirectional processor I O bit with one wire This
is possible because the DI input is only ‘‘looked-at’’ during
the MUX addressing interval while the DO line is still in a
high impedance state
3 0 REFERENCE CONSIDERATIONS
The ADC0833 is intended primarily for use in circuits requir-
ing absolute accuracy In this type of system the analog
inputs vary between very specific voltage limits and the ref-
erence voltage for the A D converter must remain stable
with time and temperature For ratiometric applications an
ADC0834 is a pin-for-pin compatible alternative since it has
a VREF input (note the ADC0834 needs one less bit of mux
addressing information)
The voltage applied to the VREF 2 pin defines the voltage
span of the analog input the difference between VIN(a)
and VIN(b) over which the 256 possible output codes ap-
ply A full-scale conversion (an all 1s output code) will result
when the voltage difference between a selected ‘‘a’’ input
and ‘‘b’’ input is approximately twice the voltage at the
VREF 2 pin This internal gain of 2 from the applied refer-
ence to the full-scale input voltage allows biasing a low volt-
age reference diode from the 5VDC converter supply To
accommodate a 5V input span only a 2 5V reference is
required The LM385 and LM336 reference diodes are good
low current devices to use with these converters The out-
put code changes in accordance with the following equa-
tion
JOutput Codee256 VIN(a) b VIN(b)
2(VREF 2)
where the output code is the decimal equivalent of the 8-bit
binary output (ranging from 0 to 255) and the term VREF 2 is
the voltage from pin 9 to ground
The VREF 2 pin is the center point of a two resistor divider
(each resistor is 3 5 kX) connected from VCC to ground
Total ladder input resistance is the sum of these two equal
resistors As shown in Figure 2 a reference diode with a
voltage less than VCC 2 can be connected without requiring
an external biasing resistor if its current requirements meet
the indicated level
The minimum value of VREF 2 can be quite small (see Typi-
cal Performance Characteristics) to allow direct conversions
of transducer outputs providing less than a 5V output span
Particular care must be taken with regard to noise pickup
circuit layout and system error voltage sources when oper-
ating with a reduced span due to the increased sensitivity of
the converter (1 LSB equals VREF 256)
VFULL-SCALEj2 4V
VFULL-SCALEj5 0V
Note
No
external
biasing
resistor
needed
if
VZ
k
VCC
2
and
IZ
min
k
VCC 2
1 75
b VZ
kX
FIGURE 2 Reference Biasing Examples
11
TL H 5607 – 7
11 Page | ||
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