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ADC0832BCN Schematic ( PDF Datasheet ) - Micro Linear Corporation

Teilenummer ADC0832BCN
Beschreibung Serial I/O 8-Bit A/D Converters with Multiplexer Options
Hersteller Micro Linear Corporation
Logo Micro Linear Corporation Logo 




Gesamt 26 Seiten
ADC0832BCN Datasheet, Funktion
May 1997
ML2281, ML2282*,
ML2284#, ML2288#
Serial I/O 8-Bit A/D Converters with
Multiplexer Options
GENERAL DESCRIPTION
The ML2281 family are 8-bit successive approximation
A/D converters with serial I/O and configurable input
multiplexers with up to 8 input channels.
All errors of the sample-and-hold, incorporated on the
ML2281 family are accounted for in the analog-to-digital
converters accuracy specification.
The voltage reference can be externally set to any value
between GND and VCC, thus allowing a full conversion
over a relatively small voltage span if desired.
The ML2281 family is an enhanced double polysilicon
CMOS pin compatible second source for the ADC0831,
ADC0832, ADC0834, and ADC0838 A/D converters. The
ML2281 series enhancements are faster conversion time,
true sample-and-hold function, superior power supply
rejection, improved AC common mode rejection, faster
digital timing, and lower power dissipation. All parameters
are guaranteed over temperature with a power supply
voltage of 5V ±10%.
BLOCK DIAGRAM
ML2281
CONTROL
AND
TIMING
CS
CLK
OUTPUT
SHIFT-REGISTER
DO
FEATURES
s Conversion time: 6µs
s Total unadjusted error: ±1/2LSB or ±1LSB
s Sample-and-hold: 375ns acquisition
s 2, 4 or 8-input multiplexer options
s 0 to 5V analog input range with single 5V
power supply
s Operates ratiometrically or with up to 5V
voltage reference
s No zero or full-scale adjust required
s ML2281 capable of digitizing a 5V, 40kHz sine wave
s Low power: 12.5mW MAX
s Superior pin compatible replacement for ADC0831,
ADC0832, ADC0834, and ADC0838
s Analog input protection: 25mA (min) per input
s Now in 8-Pin SOIC Package (ML2281, ML2282)
(* Indicates Part is Obsolete)
(# Indicates Part is End Of Life as Of July 1, 2000)
ML2288 (8-Channel SE or 4-Channel Diff Multiplexer)
ML2284 (4-Channel SE or 2-Channel Diff Multiplexer)
ML2284 (2-Channel SE or 1-Channel Diff Multiplexer)
4-BIT
INPUT
SHIFT-REGISTER
CONTROL
AND
TIMING
DI
SARS
CLK
CS
VIN+
A/D WITH SAMPLE & HOLD FUNCTION
+Σ
8pF
+
COMP
SUCCESSIVE
APPROXIMATION
REGISTER
VIN–
8pF
D/A
CONVERTER
VREF
VCC GND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COMMON
OUTPUT
SHIFT-REGISTER
DO
SE
A/D
CONVERTER
WITH
SAMPLE & HOLD
FUNCTION
DGND
SHUNT
REGULATOR
AGND VREF
VCC V+
1






ADC0832BCN Datasheet, Funktion
ML2281, ML2282, ML2284, ML2288
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
TYP
MIN NOTE 3 MAX
LIMIT
UNITS
AC ELECTRICAL CHARACTERISTICS
fCLK
tACQ
tC
SNR
THD
Clock Frequency
(Note 4)
Sample-and-Hold Acquisition
Conversion Time
Not including MUX adddressing time
Signal to Noise Ratio
ML2281
Total Harmonic Distortion
ML2281
VIN = 40kHz, 5V sine. fCLK = 1.333MHz
(fSAMPLING » 120kHz). Noise is sum of all
nonfundamental components up to 1/2
of fSAMPLING (Note 11)
VIN = 40kHz, 5V sine. fCLK = 1.333MHz
(fSAMPLING » 120kHz). THD is sum of 2,
3, 4, 5 harmonics relative to fundamental
(Note 11)
10
1.333
kHz
1/2 1/fCLK
8 1/fCLK
47 dB
–60 dB
IMD
Intermodulation Distortion
ML2281
VIN = fA + fB. fA = 40kHz, 2.5V sine.
fB = 39.8kHz, 2.5V Sine, fCLK = 1.333MHz
(fSAMPLING » 120kHz). IMD is (fA + fB),
(fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB),
(fA – 2fB) relative to fundamental (Note 11)
–60
Clock Duty Cycle
(Notes 4, 10)
40 60
dB
%
tSET-UP
CS Falling Edge or Data Input (Note 4)
Valid to CLK Rising Edge
130 ns
tHOLD
Data Input Valid after
CLK Rising Edge
(Note 4)
80 ns
tPD1,
tPD0
CLK Falling Edge to Output
Data Valid
CL = 100pF (Note 4 & 12)
Data MSB first
Data LSB first
90 200 ns
50 110 ns
t1H,
t0H
CIN
COUT
Rising Edge of CS to Data
Output and SARS Hi-Z
CL = 10pF, RL = 10k (see high impedance
test circuits) (Note 5)
Capacitance of Logic Input
CL = 100pF, RL = 2k (Note 4)
Capacitance of Logic Outputs
40 90 ns
80 160 ns
5 pF
5 pF
Note 1: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > VCC) the absolute value of current at that pin should be limited to 25mA
or less.
Note 2: 0°C to 70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by
correlation with worst-case test conditions.
Note 3: Typicals are parametric norm at 25°C.
Note 4: Parameter guaranteed and 100% production tested.
Note 5: Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
Note 6: Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors.
Note 7: Cannot be tested for ML2282.
Note 8:
For VIN³ VIN+ the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for
analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level
analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50mV, the output code will be
correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950VDC over temperature variations, initial
tolerance and loading.
Note 9: Leakage current is measured with the clock not switching.
Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the
minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs.
Note 11: Because of multiplexer addressing, test conditions for the ML2282 would be VIN = 34kHz, 5V sine (fSAMPLING » 102kHz); ML2284 VIN = 32kHz, 5V sine
(fSAMPLING » 95kHz); ML2288 VIN = 30kHz, 5V sine (fSAMPLING » 89kHz).
Note 12: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for
comparator response time.
6

6 Page









ADC0832BCN pdf, datenblatt
ML2281, ML2282, ML2284, ML2288
FUNCTIONAL DESCRIPTION
MULTIPLEXER ADDRESSING
The design of these converters utilizes a sample data
comparator structure which provides for a differential
analog input to be converted by a successive
approximation routine.
The actual voltage converted is always the difference
between an assigned “+” input terminal and a “–” input
terminal. The polarity of each input terminal of the pair
being converted indicates which line the converter expects
to be the most positive. If the assigned “+” input is less than
the “–” input, the converter responds with an all zeros
output code.
A unique input multiplexing scheme has been utilized
to provide multiple analog channels with software
configurable single ended, differential, or pseudo
differential options. The pseudo differential option will
convert the difference between the voltage at any analog
input and a common terminal. One converter package
can now accommodate ground referenced inputs and
true differential inputs as well as signals with some
arbitrary reference voltage.
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single ended or
differential. In the differential case, it also assigns the
polarity of the analog channels. Differential inputs are
restricted to adjacent channel pairs. For example, channel 0
and channel 1 may be selected as a different pair but
channel 0 or channel 1 cannot act differentially with any
other channel. In addition to selecting the differential mode,
the sign may also be selected. Channel 0 may be selected as
the positive input and channel 1 as the negative input or
vice versa. This programmability is illustrated by the MUX
addressing codes shown in Tables 1, 2, and 3.
The MUX address is shifted into the converter via the DI
input. Since the ML2281 contains only one differential
input channel with a fixed polarity assignment, it does
not require addressing.
The common input line on the ML2288 can be used as a
pseudo differential input. In this mode, the voltage on the
COM pin is treated as the “–” input for any of the other
input channels. This voltage does not have to be analog
ground; it can be any reference potential which is common
to all of the inputs. This feature is most useful in single
supply applications where the analog circuitry may be
biased at a potential other than ground and the output
signals are all referred to this potential.
Since the input configuration is under software control, it
can be modified, as required, at each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 7
illustrates these different input modes.
SINGLE-ENDED MUX MODE
MUX ADDRESS ANALOG SINGLE-ENDED CHANNEL#
SGL/ ODD/ SELECT
DIF SIGN 1 0 0 1 2 3 4 5 6 7 COM
1 0 0 0+
1 0 01
+
1 0 10
+–
1 0 11
+–
1 1 00 +
1 1 01
+
1 1 10
+–
1 1 11
+–
DIFFERENTIAL MUX MODE
MUX ADDRESS
ANALOG DIFFERENTIAL
CHANNEL-PAIR#
SGL/ ODD/ SELECT
0
1
2
3
DIF SIGN 1 0 0 1 2 3 4 5 6 7
0 0 00 + –
0 0 01
+–
0 0 10
+–
0 0 11
+–
0 1 00 – +
0 1 01
–+
0 1 10
–+
0 1 11
–+
Table 1. ML2288 MUX Addressing 8 Single-Ended
or 4 Differential Channels
SINGLE-ENDED MUX MODE
MUX ADDRESS
SGL/ ODD/ SELECT
DIF SIGN
1
10
0
10
1
11
0
11
1
0
+
CHANNEL#
123
+
+
+
COM is internally tied to AGND
DIFFERENTIAL MUX MODE
MUX ADDRESS
CHANNEL#
SGL/ ODD/ SELECT
DIF SIGN
1
0123
00
0
+–
00
1
+–
01
0
–+
01
1
–+
Table 2. ML2284 MUX Addressing 4 Single-Ended
or 2 Differential Channel
12

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