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ADC0820BCV Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC0820BCV
Beschreibung 8-Bit High Speed P Compatible A/D Converter with Track/Hold Function
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 22 Seiten
ADC0820BCV Datasheet, Funktion
June 1999
ADC0820
8-Bit High Speed µP Compatible A/D Converter with
Track/Hold Function
General Description
By using a half-flash conversion technique, the 8-bit
ADC0820 CMOS A/D offers a 1.5 µs conversion time and
dissipates only 75 mW of power. The half-flash technique
consists of 32 comparators, a most significant 4-bit ADC and
a least significant 4-bit ADC.
The input to the ADC0820 is tracked and held by the input
sampling circuitry eliminating the need for an external
sample-and-hold for signals moving at less than 100 mV/µs.
For ease of interface to microprocessors, the ADC0820 has
been designed to appear as a memory location or I/O port
without the need for external interfacing logic.
Key Specifications
n Resolution
n Conversion Time
n Low Power
n Total Unadjusted
Error
8 Bits
2.5 µs Max (RD Mode)
1.5 µs Max (WR-RD Mode)
75 mW Max
±12 LSB and ± 1 LSB
Features
n Built-in track-and-hold function
n No missing codes
n No external clocking
n Single supply — 5 VDC
n Easy interface to all microprocessors, or operates
stand-alone
n Latched TRI-STATE® output
n Logic inputs and outputs meet both MOS and T2L
voltage level specifications
n Operates ratiometrically or with any reference value
equal to or less than VCC
n 0V to 5V analog input voltage range with single 5V
supply
n No zero or full-scale adjust required
n Overflow output available for cascading
n 0.3" standard width 20-pin DIP
n 20-pin molded chip carrier package
n 20-pin small outline package
n 20-pin shrink small outline package (SSOP)
Connection and Functional Diagrams
Dual-In-Line, Small Outline
and SSOP Packages
Molded Chip Carrier
Package
Top View
DS005501-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS005501
DS005501-33
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ADC0820BCV Datasheet, Funktion
TRI-STATE Test Circuits and Waveforms
t1H
DS005501-3
t0H
tr=20 ns
Timing Diagrams
DS005501-5
tr=20 ns
DS005501-4
DS005501-6
Note: On power-up the state of INT can be high or low.
FIGURE 2. RD Mode (Pin 7 is Low)
DS005501-7
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ADC0820BCV pdf, datenblatt
1.0 Functional Description (Continued)
Note: MS means most significant
LS means least significant
DS005501-20
FIGURE 11. Operating Sequence (WR-RD Mode)
OTHER INTERFACE CONSIDERATIONS
In order to maintain conversion accuracy, WR has a maxi-
mum width spec of 50 µs. When the MS flash ADC’s
sampled-data comparators (Section 1.2) are in comparison
mode (WR is low), the input capacitors (C, Figure 8 ) must
hold their charge. Switch leakage and inverter bias current
can cause errors if the comparator is left in this phase for too
long.
Since the MS flash ADC enters its zeroing phase at the end
of a conversion (Section 1.3), a new conversion cannot be
started until this phase is complete. The minimum spec for
this time (tP, Figures 2, 3, 4, 5 ) is 500 ns.
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