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ADC08161CIWM Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC08161CIWM
Beschreibung 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 15 Seiten
ADC08161CIWM Datasheet, Funktion
June 1999
ADC08161
500 ns A/D Converter with S/H Function and
2.5V Bandgap Reference
General Description
Using a patented multi-step A/D conversion technique, the
8-bit ADC08161 CMOS A/D converter offers 500 ns conver-
sion time, internal sample-and-hold (S/H), a 2.5V bandgap
reference, and dissipates only 100 mW of power. The
ADC08161 performs an 8-bit conversion with a 2-bit voltage
estimator that generates the 2 MSBs and two low-resolution
(3-bit) flashes that generate the 6 LBSs.
Input signals are tracked and held by the input sampling cir-
cuitry, eliminating the need for an external sample-and-hold.
The ADC08161 can perform accurate conversions of
full-scale input signals at frequencies from DC to typically
more than 300 kHz (full power bandwidth) without the need
of an external sample-and-hold (S/H).
For ease of interface to microprocessors, this part has been
designed to appear as a memory location or I/O port without
the need for external interfacing logic.
Key Specifications
n Resolution
n Conversion time (tCONV)
n Full power bandwidth
n Throughput rate
n Power dissipation
n Total unadjusted error
8 Bits
560 ns max (WR-RD Mode)
300 kHz (typ)
1.5 MHz min
100 mW max
±12 LSB and ±1 LSB max
Features
n No external clock required
n Analog input voltage range from GND to V+
n 2.5V bandgap reference
Applications
n Mobile telecommunications
n Hard-disk drives
n Instrumentation
n High-speed data acquisition systems
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011149
DS011149-1
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ADC08161CIWM Datasheet, Funktion
Bandgap Reference Electrical Characteristics (Continued)
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply voltage (VIN < GND or VIN > V+), the absolute value of the current at that pin should be
limited to 5 mA or less. The 20 mA package input current specification limits the number of pins that can exceed the power supply boundaries with a 5 mA current
limit to four.
Note 4: The power dissipation of this device under normal operation should never exceed 875 mW (Quiescent Power Dissipation + TTL Loads on the digital outputs).
Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (e.g., when any input or output ex-
ceeds the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX (maximum junction temperature), θJA
(package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJMAX
− TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 105˚C and θJA = 85˚C/W.
Note 5: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices.
Note 6: Human body model, 100 pF discharged through a 1.5 kresistor.
Note 7: Typicals are at 25˚C and represent most likely parametric norm.
Note 8: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 9: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 10: Two on-chip diodes are tied to each analog input and are reversed biased during normal operation. One is connected to V+ and the other is connected to
GND. They will become forward biased and conduct when an analog input voltage is equal to or greater than one diode drop above V+ or below GND. Therefore,
caution should be exercised when testing with V+ = 4.5V. Analog inputs with magnitudes equal to 5V can cause an input diode to conduct, especially at elevated tem-
peratures. This can create conversion errors for analog signals near full-scale. The specification allows 50 mV forward bias on either diode; e.g., the output code will
be correct as long as the analog input signal does not exceed the supply voltage by more than 50 mV. Exceeding this range on an unselected channel will corrupt
the reading of a selected channel. An absolute analog input signal voltage range of 0V VIN 5V can be achieved by ensuring that the minimum supply voltage ap-
plied to V+ is 4.950V over temperature variations, initial tolerance, and loading.
Note 11: Off-channel leakage current is measured on the on-channel selection.
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ADC08161CIWM pdf, datenblatt
Application Information (Continued)
tween 0 and 3/16 of VREF (VREF = VREF+ − VREF−), the esti-
mator decoder instructs the comparator multiplexer to select
the eight tap points between 8/256 and 2/8 of VREF and con-
nects them to the eight flash comparators. The first flash
conversion is now performed, producing the five MSBs of
data.
The remaining three LSBs are generated next using the
same eight comparators that were used for the first flash
conversion. As determined by the results of the MSB flash, a
voltage from the MSB Ladder equivalent to the magnitude of
the five MSBs is subtracted from the analog input voltage as
the upper switch is moved from position one to position two.
The resulting remainder voltage is applied to the eight flash
comparators and, with the lower switch in position two, com-
pared with the eight tap points from the LSB Ladder.
By using the same eight comparators for both flash conver-
sions, the number of comparators needed by the multi-step
converter is significantly reduced when compared to stan-
dard half-flash techniques.
Voltage Estimator errors as large as 1/16 of VREF(16 LSBs)
will be corrected since the flash comparators are connected
to ladder voltages that extend beyond the range specified by
the Voltage Estimator. For example, if 7/16 VREF < VIN <
9/16 VREF the Voltage Estimator’s comparators tied to the
tap points below 9/16 VREF will output “1”s (000111). This is
decoded by the estimator decoder to “10”. The eight flash
comparators will be placed at the MSB Ladder tap points be-
tween 38 VREF and 58 VREF. The overlap of 1/16 VREF on
each side of the Voltage Estimator’s span will automatically
correct an error of up to 16 LSBs (16 LSBs = 312.5 mV for
VREF = 5V). If the first flash conversion determines that the
input voltage is between 38 VREF and 4/8 VREF − LSB/2, the
Voltage Estimator’s output code will be corrected by sub-
tracting “1”. This results in a corrected value of “01”. If the
first flash conversion determines that the input voltage is be-
tween 8/16 VREF − LSB/2 and 58 VREF, the Voltage Estima-
tor’s output code remains unchanged.
After correction, the 2-bit data from both the Voltage Estima-
tor and the first flash conversion are decoded to produce the
five MSBs. Decoding is similar to that of a 5-bit flash con-
verter since there are 32 tap points on the MSB Ladder.
However, 31 comparators are not needed since the Voltage
Estimator places the eight comparators along the MSB Lad-
der where reference tap voltages are present that fall above
and below the magnitude of VIN. Comparators are not
needed outside this selected range. If a comparator’s output
is a “0”, all comparators above it will also have outputs of “0”
and if a comparator’s output is a “1”, all comparators below it
will also have outputs of “1”.
2.0 DIGITAL INTERFACE
The ADC08161 has two basic interface modes which are se-
lected by connecting the MODE pin to a logic high or low.
2.1 RD Mode
With a logic low applied to the MODE pin, the converter is set
to Read mode. In this configuration (Figure 1), a complete
conversion is done by pulling RD low, and holding low, until
the conversion is complete and output data appears. This
typically takes 655 ns. The INT (interrupt) line goes low at
the end of conversion. A typical delay of 50 ns is needed be-
tween the rising edge of CS (after the end of a conversion)
and the start of the next conversion (by pulling RD low). The
RDY output goes low after the falling edge of CS and goes
high at the end-of-conversion. It can be used to signal a pro-
cessor that the converter is busy or serve as a system Trans-
fer Acknowledge signal.
2.2 RD Mode Pipelined Operation
Applications that require shorter RD pulse widths than those
used in the Read mode as described above can be achieved
by setting RD’s width between 200 ns–400 ns (Figure 5). RD
pulse widths outside this range will create conversion linear-
ity errors. These errors are caused by exercising internal in-
terface logic circuitry using CS and/or RD during a conver-
sion.
When RD goes low, a conversion is initiated and the data
from the previous conversion is available on the DB0–DB7
outputs. Reading DB0–DB7 for the first two times after
power-up produces random data. The data will be valid dur-
ing the third RD pulse that occurs after the first conversion.
2.3 WR-RD (WR then RD ) Mode
The ADC08161 is in the WR-RD mode with the MODE pin
tied high. A conversion starts on the rising edge of the WR
signal. There are two options for reading the output data
which relate to interface timing. If an interrupt-driven scheme
is desired, the user can wait for the INT output to go low be-
fore reading the conversion result (Figure 3). Typically, INT
will go low 690 ns, maximum, after WR’s rising edge. How-
ever, if a shorter conversion time is desired, the processor
need not wait for INT and can exercise a read after only 350
ns (Figure 2). If RD is pulled low before INT goes low, INT
will immediately go low and data will appear at the outputs.
This is the fastest operating mode (tRD tINTL) with a conver-
sion time, including data access time, of 560 ns. Allowing
100 ns for reading the conversion data and the delay be-
tween conversions gives a total throughput time of 660 ns
(throughput rate of 1.5 MHz).
2.4 WR-RD Mode with Reduced Interface System
Connection
CS and RD can be tied low, using only WR to control the
start of conversion for applications that require reduced digi-
tal interface while operating in the WR-RD mode (Figure 4).
Data will be valid approximately 705 ns following WR’s rising
edge.
3.0 REFERENCE INPUTS
The ADC08161’s two VREF inputs are fully differential and
define the zero to full-scale input range of the A to D con-
verter. This allows the designer to vary the span of the ana-
log input since this range will be equivalent to the voltage dif-
ference between VREF+and VREF−. Transducers that have
outputs that minimum output voltages above GND can also
be compensated by connecting VREF− to a voltage that is
equal to this minimum voltage. By reducing VREF (VREF =
VREF+–VREF−) to less than 5V, the sensitivity of the converter
can be increased (i.e., if VREF = 2.5V, then 1 LSB = 9.8 mV).
The reference arrangement also facilitates ratiometric opera-
tion and in may cases the power supply can be used for
transducer power as well as the VREF source. Ratiometric
operation is achieved by connecting VREF− to GND and con-
necting VREF+ and a transducer’s power supply input to V+.
The ADC08161s accuracy degrades when VREF+–|VREF−| is
less than 2.0V.
The voltage at VREF− sets the input level that produces a
digital output of all zeroes. Through VIN is not itself differen-
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