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ADC0811BCV Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC0811BCV
Beschreibung 8-Bit Serial I/O A/D Converter With 11-Channel Multiplexer
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 14 Seiten
ADC0811BCV Datasheet, Funktion
December 1994
ADC0811 8-Bit Serial I O A D Converter
With 11-Channel Multiplexer
General Description
The ADC0811 is an 8-Bit successive approximation A D
converter with simultaneous serial I O The serial input con-
trols an analog multiplexer which selects from 11 input
channels or an internal half scale test voltage
An input sample-and-hold is implemented by a capacitive
reference ladder and sampled data comparator This allows
the input signal to vary during the conversion cycle
Separate serial I O and conversion clock inputs are provid-
ed to facilitate the interface to various microprocessors
Features
Y Separate asynchronous converter clock and serial data
I O clock
Y 11-Channel multiplexer with 4-Bit serial address logic
Y Built-in sample and hold function
Y Ratiometric or absolute voltage referencing
Y No zero or full-scale adjust required
Y Internally addressable test voltage
Y 0V to 5V input range with single 5V power supply
Y TTL MOS input output compatible
Y 0 3 standard width 20-pin dip or 20-pin molded chip
carrier
Key Specifications
Y Resolution
Y Total unadjusted error
Y Single supply
Y Low Power
Y Conversion Time
8-Bits
g LSB and g 1LSB
5VDC
15 mW
32 mS
Connection Diagrams
Dual-In-Line Package
Functional Diagram
Top View
TL H 5587–1
Molded Chip Carrier (PCC) Package
Top View
TL H 5587–2
Order Number ADC0811J N V
See NS Packages J20A N20A V20A
Use Ordering Information
C1995 National Semiconductor Corporation TL H 5587
TL H 5587 – 3
RRD-B30M115 Printed in U S A






ADC0811BCV Datasheet, Funktion
Timing Diagrams
D0 ‘‘TRI-STATE’’ Rise Fall Times
D0 Low to High State
TL H 5587–13
TL H 5587 – 14
Timing with a continuous SCLK
D0 High to Low State
TL H 5587 – 15
Strobing CS High and Low will abort the present conversion and initiate a new serial I O exchange
Timing with a gated SCLK and CS Continuously Low
TL H 5587 – 11
Using CS To TRI-STATE D0
TL H 5587 – 9
Note Strobing CS Low during this time interval will abort the conversion in process
TL H 5587 – 10
6

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