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ADC0809 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC0809
Beschreibung 8-Bit uP Compatible A/D Converters with 8-Channel Multiplexer
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 16 Seiten
ADC0809 Datasheet, Funktion
ADC0808/ADC0809
July 8, 2009
8-Bit μP Compatible A/D Converters with 8-Channel
Multiplexer
General Description
The ADC0808, ADC0809 data acquisition component is a
monolithic CMOS device with an 8-bit analog-to-digital con-
verter, 8-channel multiplexer and microprocessor compatible
control logic. The 8-bit A/D converter uses successive ap-
proximation as the conversion technique. The converter fea-
tures a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a successive
approximation register. The 8-channel multiplexer can direct-
ly access any of 8-single-ended analog signals.
The device eliminates the need for external zero and full-scale
adjustments. Easy interfacing to microprocessors is provided
by the latched and decoded multiplexer address inputs and
latched TTL TRI-STATE outputs.
The design of the ADC0808, ADC0809 has been optimized
by incorporating the most desirable aspects of several A/D
conversion techniques. The ADC0808, ADC0809 offers high
speed, high accuracy, minimal temperature dependence, ex-
cellent long-term accuracy and repeatability, and consumes
minimal power. These features make this device ideally suit-
ed to applications from process and machine control to con-
sumer and automotive applications. For 16-channel multi-
plexer with common output (sample/hold port) see ADC0816
data sheet. (See AN-247 for more information.)
Features
Easy interface to all microprocessors
Operates ratiometrically or with 5 VDC or analog span
adjusted voltage reference
No zero or full-scale adjust required
8-channel multiplexer with address logic
0V to VCC input range
Outputs meet TTL voltage level specifications
ADC0808 equivalent to MM74C949
ADC0809 equivalent to MM74C949-1
Key Specifications
Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time
8 Bits
±½ LSB and ±1 LSB
5 VDC
15 mW
100 μs
Block Diagram
See Ordering Information
© 2009 National Semiconductor Corporation 5672
567201
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ADC0809 Datasheet, Funktion
FIGURE 1. Resistor Ladder and Switch Tree
567202
567213
FIGURE 2. 3-Bit A/D Transfer Curve
567214
FIGURE 3. 3-Bit A/D Absolute Accuracy Curve
FIGURE 4. Typical Error Curve
567215
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ADC0809 pdf, datenblatt
RA=RB
*Ratiometric transducers
FIGURE 13. Symmetrically Centered Reference
567227
3.0 CONVERTER EQUATIONS
The transition between adjacent codes N and N+1 is given
by:
The center of an output code N is given by:
(2)
(3)
The output code N for an arbitrary input are the integers within
the range:
Where:
VIN=Voltage at comparator input
VREF(+)=Voltage at Ref(+)
VREF(−)=Voltage at Ref(−)
VTUE=Total unadjusted error voltage (typically
(4)
VREF(+)÷512)
4.0 ANALOG COMPARATOR INPUTS
The dynamic comparator input current is caused by the peri-
odic switching of on-chip stray capacitances. These are con-
nected alternately to the output of the resistor ladder/switch
tree network and to the comparator input as part of the oper-
ation of the chopper stabilized comparator.
The average value of the comparator input current varies di-
rectly with clock frequency and with VIN as shown in
Figure 6.
If no filter capacitors are used at the analog inputs and the
signal source impedances are low, the comparator input cur-
rent should not introduce converter errors, as the transient
created by the capacitance discharge will die out before the
comparator output is strobed.
If input filter capacitors are desired for noise reduction and
signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteris-
tics of a DC bias current whose effect can be predicted
conventionally.
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