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ADC0806 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC0806
Beschreibung 8-Bit/ 20 MSPS to 60 MSPS/ 1.3 mW/MSPS A/D Converter
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 19 Seiten
ADC0806 Datasheet, Funktion
January 2003
ADC08060
8-Bit, 20 MSPS to 60 MSPS, 1.3 mW/MSPS A/D Converter
General Description
The ADC08060 is a low-power, 8-bit, monolithic analog-to-
digital converter with an on-chip track-and-hold circuit. Opti-
mized for low cost, low power, small size and ease of use,
this product operates at conversion rates of 20 MSPS to 70
MSPS with outstanding dynamic performance over its full
operating range while consuming just 1.3 mW per MHz of
clock frequency. That’s just 78 mW of power at 60 MSPS.
Raising the PD pin puts the ADC08060 into a Power Down
mode where it consumes just 1 mW.
The unique architecture achieves 7.5 Effective Bits with
25 MHz input frequency. The excellent DC and AC charac-
teristics of this device, together with its low power consump-
tion and single +3V supply operation, make it ideally suited
for many imaging and communications applications, includ-
ing use in portable equipment. Furthermore, the ADC08060
is resistant to latch-up and the outputs are short-circuit proof.
The top and bottom of the ADC08060’s reference ladder are
available for connections, enabling a wide range of input
possibilities. The digital outputs are TTL/CMOS compatible
with a separate output power supply pin to support interfac-
ing with 3V or 2.5V logic. The digital inputs (CLK and PD) are
TTL/CMOS compatible.
The ADC08060 is offered in a 24-lead plastic package
(TSSOP) and is specified over the industrial temperature
range of −40˚C to +85˚C.
Features
n Single-ended input
n Internal sample-and-hold function
n Low voltage (single +3V) operation
n Small package
n Power-down feature
Key Specifications
n Resolution
8 bits
n Maximum sampling frequency
60 MSPS (min)
n DNL
0.4 LSB (typ)
n ENOB
7.5 bits (typ) at fIN = 25 MHz
n THD
−60 dB (typ)
n No missing codes
Guaranteed
n Power Consumption
n Operating
1.3 mW/MSPS (typ)
n Power down
1 mW (typ)
Applications
n Digital imaging systems
n Communication systems
n Portable instrumentation
n Viterbi decoders
n Set-top boxes
Pin Configuration
© 2003 National Semiconductor Corporation DS200062
20006201
www.national.com






ADC0806 Datasheet, Funktion
Converter Electrical Characteristics (Continued)
The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50%
duty cycle. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
POWER SUPPLY CHARACTERISTICS
DC Input
76 96 mW (max)
PC Power Consumption
fIN = 10 MHz, VIN = FS − 3 dB,
PD = Low
88
mW
CLK Low, PD = Hi
0.6 mW
PSRR1 Power Supply Rejection Ratio
PSRR2 Power Supply Rejection Ratio
FSE change with 2.7V to 3.3V change
in VA
SNR change with 200 mV at 200 kHz
on supply
54
45
dB
dB
AC ELECTRICAL CHARACTERISTICS
fC1 Maximum Conversion Rate
fC2 Minimum Conversion Rate
tCL Minimum Clock Low Time
tCH Minimum Clock High Time
tOH Output Hold Time
tOD Output Delay
Pipeline Delay (Latency)
CLK Rise to Data Invalid
CLK Rise to Data Valid
70 60 MHz (min)
20 MHz
6.7 ns (min)
6.7 ns (min)
4.4 ns
8.2 12 ns (max)
2.5 Clock Cycles
tAD Sampling (Aperture) Delay
tAJ Aperture Jitter
CLK Fall to Acquisition of Data
1.5
2
ns
ps rms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or DR VD), the current at that pin
should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input
current of 25 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. In the 24-pin
TSSOP, θJA is 92˚C/W, so PDMAX = 1,358 mW at 25˚C and 435 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of
this device under normal operation will typically be about 180 mW (88 mW quiescent power +12 mW reference ladder power). The values for maximum power
dissipation listed above will be reached only when the ADC08060 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power
supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kresistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device.
However, errors in the A/D conversion can occur if the input goes above DR VD or below GND by more than 100 mV. For example, if VA is 2.7VDC the full-scale input
voltage must be 2.6VDC to ensure accurate conversions.
20006207
Note 8: To guarantee accuracy, it is required that VA and DR VD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.
Note 9: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
Level).
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ADC0806 pdf, datenblatt
Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after
the fall of the clock input for the sampling switch to open. The
Sample/Hold circuit effectively stops capturing the input sig-
nal and goes into the “hold” mode tAD after the clock goes
low.
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as noise at the
output.
CLOCK DUTY CYCLE is the ratio of the time that the clock
wavesform is at a logic high to the total time of one clock
period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 60 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD –
1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL-POWER BANDWIDTH is the frequency at which the
reconstructed output fundamental drops 3 dB below its low
frequency value for a full scale input.
FULL-SCALE ERROR is a measure of how far the last code
transition is from the ideal 112 LSB below VRT and is defined
as:
Vmax + 1.5 LSB – VRT
where Vmax is the voltage at which the transition to the
maximum (full scale) code occurs.
INTEGRAL NON-LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from zero
scale (12 LSB below the first code transition) through positive
full scale (12 LSB above the last code transition). The devia-
tion of any given code from this straight line is measured
from the center of that code value. The end point test method
is used. Measured at 60 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of the interaction
between two sinusoidal frequencies that are applied to the
ADC input at the same time. IMD is the ratio of the power in
the second and third order intermodulation products to the
total power in the original frequencies.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes
cannot be reached with any input value.
POWER SUPPLY REJECTION RATIO (PSRR) is a mea-
sure of how well the ADC rejects a change in the power
supply voltage. For the ADC08060, PSRR1 is the ratio of the
change in dc power supply voltage to the resulting change in
Full-Scale Error, expressed in dB. PSRR2 is a measure of
how well an a.c. signal riding upon the power supply is
rejected and is here defined as:
where SNR0 is the SNR measured with no noise or signal on
the supply lines and SNR1 is the SNR measured with a 200
kHz, 200 mVP-P signal riding upon the supply lines.
OUTPUT DELAY is the time delay after the rising edge of
the input clock before the data changes at the output pins.
OUTPUT HOLD TIME is the length of time that the output
data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the Output Delay.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal frequency at the
output to the rms value of the sum of all other spectral
components below one-half the sampling frequency, not in-
cluding harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
input signal frequency at the output to the rms value of all of
the other spectral components below half the clock fre-
quency, including harmonics but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal frequency at the output and the peak spurious signal,
where a spurious signal is any signal present in the output
spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB, of the total of the first nine harmonic levels at
the output to the level of the fundatmental at the output. THD
is calculated as
where f1 is the RMS power of the fundamental (input) fre-
quency and f2 through f10 is the power in the first 9 harmon-
ics in the output spectrum.
ZERO SCALE OFFSET ERROR is the error in the input
voltage required to cause the first code transition. It is de-
fined as
VOFF = VZT − VRB
where VZT is the first code transition input voltage.
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