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ADC08034 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC08034
Beschreibung 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options/
Voltage Reference/ and Track/Hold Function
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 24 Seiten
ADC08034 Datasheet, Funktion
June 1999
ADC08031/ADC08034/ADC08038
8-Bit High-Speed Serial I/O A/D Converters with
Multiplexer Options, Voltage Reference, and Track/Hold
Function
General Description
The ADC08031/ADC08032/ADC08034/ADC08038 are 8-bit
successive approximation A/D converters with serial I/O and
configurable input multiplexers with up to 8 channels. The
serial I/O is configured to comply with the NSC MICROW-
IREserial data exchange standard for easy interface to the
COPSfamily of controllers, and can easily interface with
standard shift registers or microprocessors.
The ADC08034 and ADC08038 provide a 2.6V band-gap de-
rived reference. For devices offering guaranteed voltage ref-
erence performance over temperature see ADC08131,
ADC08134 and ADC08138.
A track/hold function allows the analog voltage at the positive
input to vary during the actual A/D conversion.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or
pseudo-differential modes. In addition, input voltage spans
as small as 1V can be accommodated.
Applications
n Digitizing automotive sensors
n Process control monitoring
n Remote sensing in noisy environments
n Instrumentation
n Test systems
n Embedded diagnostics
Features
n Serial digital data link requires few I/O pins
n Analog input track/hold function
n 2-, 4-, or 8-channel input multiplexer options with
address logic
n 0V to 5V analog input range with single 5V power
supply
n No zero or full scale adjustment required
n TTL/CMOS input/output compatible
n On chip 2.6V band-gap reference
n 0.3" standard width 8-, 14-, or 20-pin DIP package
n 14-, 20-pin small-outline packages
Key Specifications
n Resolution
8 bits
n Conversion time (fC= 1 MHz)
8µs (max)
n Power dissipation
20mW (max)
n Single supply
n Total unadjusted error
5VDC (±5%)
±12 LSB and ±1LSB
n No missing codes over temperature
Ordering Information
Industrial (−40˚C TA +85˚C)
ADC08031CIN
ADC08031CIWM, ADC08034CIWM
ADC08038CIWM
Package
N08E
M14B
M20B
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
COPSmicrocontrollers and MICROWIREare trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS010555
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ADC08034 Datasheet, Funktion
Leakage Current Test Circuit
TRI-STATE Test Circuits and Waveforms
t1H
DS010555-7
t0H
DS010555-38
DS010555-39
Timing Diagrams
DS010555-40
Data Input Timing
DS010555-41
DS010555-10
*To reset these devices, CLK and CS must be simultaneously high for a period of tSELECT or greater. Otherwise these devices are compatible with industry
standards ADC0831/2/4/8.
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ADC08034 pdf, datenblatt
Functional Description (Continued)
TABLE 4. MUX Addressing: ADC08034
Single-Ended MUX Mode
MUX Address
START
SGL/
ODD/
DIF SIGN
1 10
1 10
1 11
1 11
SELECT
1
0
1
0
1
Channel #
0123
+
+
+
+
COM is internally tied to AGND
Since the input configuration is under software control, it can
be modified as required before each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 1 illus-
trates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50mV below ground to 50mV above VCC (typically 5V) with-
out degrading conversion accuracy.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system im-
provements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.
1. A conversion is initiated by pulling the CS (chip select)
line low. This line must be held low for the entire conver-
sion. The converter is now waiting for a start bit and its
MUX assignment word.
2. On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register.
The start bit is the first logic “1” that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX as-
signment word.
3. When the start bit has been shifted into the start location
of the MUX register, the input channel has been as-
signed and a conversion is about to begin. An interval of
12 clock period (where nothing happens) is automatically
inserted to allow the selected MUX channel to settle.
The SARS line goes high at this time to signal that a con-
version is now in progress and the DI line is disabled (it
no longer accepts data).
4. The data out (DO) line now comes out of TRI-STATE
and provides a leading zero for this one clock period of
MUX settling time.
5. During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages gener-
ated internally from a ratioed capacitor array (first 5 bits)
and a resistor ladder (last 3 bits). After each comparison
the comparator’s output is shipped to the DO line on the
falling edge of CLK. This data is the result of the conver-
sion being shifted out (with the MSB first) and can be
read by the processor immediately.
6. After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this 12 clock cycle later.
7. The stored data in the successive approximation register
is loaded into an internal shift register. If the programmer
prefers the data can be provided in an LSB first format
[this makes use of the shift enable (SE) control line]. On
the ADC08038 the SE line is brought out and if held high
the value of the LSB remains valid on the DO line. When
SE is forced low the data is clocked out LSB first. On de-
vices which do not include the SE control line, the data,
LSB first, is automatically shifted out the DO line after
the MSB first data stream. The DO line then goes low
and stays low until CS is returned high. The ADC08031
is an exception in that its data is only output in MSB first
format.
8. All internal registers are cleared when the CS line is high
and the tSELECT requirement is met. See Data Input Tim-
ing under Timing Diagrams. If another conversion is de-
sired CS must make a high to low transition followed by
address information.
The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire.
This is possible because the DI input is only “looked-at”
during the MUX addressing interval while the DO line is
still in a high impedance state.
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