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ADC0803 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer ADC0803
Beschreibung 8-Bit/ Microprocessor-Compatible/ A/D Converters
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 17 Seiten
ADC0803 Datasheet, Funktion
®
Data Sheet
ADC0803, ADC0804
August 2002
FN3094.4
8-Bit, Microprocessor-Compatible, A/D
Converters
The ADC080X family are CMOS 8-Bit, successive-
approximation A/D converters which use a modified
potentiometric ladder and are designed to operate with the
8080A control bus via three-state outputs. These converters
appear to the processor as memory locations or I/O ports,
and hence no interfacing logic is required.
The differential analog voltage input has good common-
mode-rejection and permits offsetting the analog zero-input-
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Typical Application Schematic
ANY
µPROCESSOR
1 CS
2 RD
V+ 20 +5V 150pF
CLK R 19
3 WR CLK IN 4 10K
5 INTR
11 DB7
12 DB6
13 DB5
14 DB4
15 DB3
16 DB2
17 DB1
18 DB0
VIN (+)
VIN (-)
AGND
6
7
8
DIFF
INPUTS
VREF/2 9 VREF/2
DGND 10
8-BIT RESOLUTION
OVER ANY
DESIRED
ANALOG INPUT
VOLTAGE RANGE
Features
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . <100µs
• Easy Interface to Most Microprocessors
• Will Operate in a “Stand Alone” Mode
• Differential Analog Voltage Inputs
• Works with Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• Analog Voltage Input Range
(Single + 5V Supply) . . . . . . . . . . . . . . . . . . . . . . 0V to 5V
• No Zero-Adjust Required
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
Pinout
ADC0803, ADC0804
(PDIP)
TOP VIEW
CS 1
RD 2
WR 3
CLK IN 4
INTR 5
VIN (+) 6
VIN (-) 7
AGND 8
VREF/2 9
DGND 10
20 V+ OR VREF
19 CLK R
18 DB0 (LSB)
17 DB1
16 DB2
15 DB3
14 DB4
13 DB5
12 DB6
11 DB7 (MSB)
Ordering Information
PART NUMBER
ADC0803LCN
ADC0804LCN
ERROR
±1/2 LSB
±1 LSB
EXTERNAL CONDITIONS
VREF/2 Adjusted for Correct Full Scale
Reading
VREF/2 = 2.500VDC (No Adjustments)
TEMP. RANGE (oC)
PACKAGE
0 to 70
20 Ld PDIP
0 to 70
20 Ld PDIP
PKG. NO
E20.3
E20.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved






ADC0803 Datasheet, Funktion
ADC0803, ADC0804
Typical Performance Curves (Continued)
7
6 V+ = 4.5V
5
4
3
2 V+ = 5V
1
0 V+ = 6V
0
400
800
1200
1600
2000
fCLK (kHz)
FIGURE 6. FULL SCALE ERROR vs fCLK
16
VIN(+) = VIN(-) = 0V
14 ASSUMES VOS = 2mV
12
THIS SHOWS THE NEED
FOR A ZERO ADJUSTMENT
IF THE SPAN IS REDUCED
10
8
6
4
2
0
0.01
0.1 1.0
VREF/2 (V)
5
FIGURE 7. EFFECT OF UNADJUSTED OFFSET ERROR
8
V+ = 5V
7
DATA OUTPUT
BUFFERS
6
5 ISOURCE
VOUT = 2.4V
4
3
2
-50
-ISINK
VOUT = 0.4V
-25 0
25 50 75 100
TA AMBIENT TEMPERATURE (oC)
125
FIGURE 8. OUTPUT CURRENT vs TEMPERATURE
Timing Diagrams
1.6
fCLK = 640kHz
1.5
V+ = 5.5V
1.4
1.3
V+ = 5.0V
1.2
1.1 V+ = 4.5V
1.0
-50
-25 0 25 50 75 100
TA AMBIENT TEMPERATURE (oC)
125
FIGURE 9. POWER SUPPLY CURRENT vs TEMPERATURE
CS
WR
ACTUAL INTERNAL
STATUS OF THE
CONVERTER
tWI
tW(WR)I
(LAST DATA READ)
INTR
(LAST DATA NOT READ)
“BUSY”
“NOT BUSY”
1 TO 8 x 1/fCLK
INTERNAL TC
tVI
FIGURE 10A. START CONVERSION
DATA IS VALID IN
OUTPUT LATCHES
INTR
ASSERTED
1/2 fCLK
6

6 Page









ADC0803 pdf, datenblatt
ADC0803, ADC0804
Finally, if time is short and capacitive loading is high, external
bus drivers must be used. These can be three-state buffers
(low power Schottky is recommended, such as the 74LS240
series) or special higher-drive-current products which are
designed as bus drivers. High-current bipolar bus drivers
with PNP inputs are recommended.
Power Supplies
Noise spikes on the V+ supply line can cause conversion
errors as the comparator will respond to this noise. A
low-inductance tantalum filter capacitor should be used
close to the converter V+ pin, and values of 1µF or greater
are recommended. If an unregulated voltage is available in
the system, a separate 5V voltage regulator for the converter
(and other analog circuitry) will greatly reduce digital noise
on the V+ supply. An lCL7663 can be used to regulate such
a supply from an input as low as 5.2V.
Wiring and Hook-Up Precautions
Standard digital wire-wrap sockets are not satisfactory for
breadboarding with this A/D converter. Sockets on PC
boards can be used. All logic signal wires and leads should
be grouped and kept as far away as possible from the
analog signal leads. Exposed leads to the analog inputs can
cause undesired digital noise and hum pickup; therefore,
shielded leads may be necessary in many applications.
A single-point analog ground should be used which is
separate from the logic ground points. The power supply
bypass capacitor and the self-clockIng capacitor (if used)
should both be returned to digital ground. Any VREF/2
bypass capacitors, analog input filter capacitors, or input
signal shielding should be returned to the analog ground
point. A test for proper grounding is to measure the zero
error of the A/D converter. Zero errors in excess of 1/4 LSB
can usually be traced to improper board layout and wiring
(see Zero Error for measurement). Further information can
be found in Application Note AN018.
Testing the A/D Converter
There are many degrees of complexity associated with testing
an A/D converter. One of the simplest tests is to apply a
known analog input voltage to the converter and use LEDs to
display the resulting digital output code as shown in Figure 18.
For ease of testing, the VREF/2 (pin 9) should be supplied
with 2.560V and a V+ supply voltage of 5.12V should be
used. This provides an LSB value of 20mV.
If a full scale adjustment is to be made, an analog input
voltage of 5.090V (5.120 - 11/2 LSB) should be applied to
the VIN(+) pin with the VIN(-) pin grounded. The value of the
VREF/2 input voltage should be adjusted until the digital
output code is just changing from 1111 1110 to 1111 1111.
This value of VREF/2 should then be used for all the tests.
The digital-output LED display can be decoded by dividing
the 8 bits into 2 hex characters, one with the 4 most-
significant bits (MS) and one with the 4 least-significant bits
(LS). The output is then interpreted as a sum of fractions
times the full scale voltage:
VOUT
=
M--1---6-S--
+
2--L--5-S--6--
(5
.12
)V
.
10k
150pF
N.O.
START
VIN (+) 0.1µF
AGND
2.560V
VREF/2
0.1µF
1
2
3
4
5 ADC0803-
6 ADC0804
7
8
9
10
DGND
20 + 5.120V
19
10µF
TANTALUM
18 LSB
17
16
15
5V
14
13
12
11 MSB
1.3kLEDs
(8) (8)
FIGURE 18. BASIC TESTER FOR THE A/D
For example, for an output LED display of 1011 0110, the
MS character is hex B (decimal 11) and the LS character is
hex (and decimal) 6, so:
VOUT
=
11----16--
+
2----56---6--
( 5 .12 )
=
3 .64V.
Figures 19 and 20 show more sophisticated test circuits.
ANALOG
INPUTS
8-BIT
A/D UNDER
TEST
“B”
R
R
“A”
10-BIT
DAC
VANALOG OUTPUT
R
-
A1 +
100R
R
“C”
-
+ A2
100X ANALOG
ERROR VOLTAGE
FIGURE 19. A/D TESTER WITH ANALOG ERROR OUTPUT. THIS
CIRCUIT CAN BE USED TO GENERATE “ERROR
PLOTS” OF FIGURE 11.
DIGITAL
INPUTS
10-BIT
DAC
VANALOG
A/D UNDER
TEST
DIGITAL
OUTPUTS
FIGURE 20. BASIC “DIGITAL” A/D TESTER
Typical Applications
Interfacing 8080/85 or Z-80 Microprocessors
12

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