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AD9995 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9995
Beschreibung 12-Bit CCD Signal Processor with Precision Timing Generator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 60 Seiten
AD9995 Datasheet, Funktion
12-Bit CCD Signal Processor with
Precision Timing Generator
AD9995
FEATURES
6-Phase Vertical Transfer Clock Support
Correlated Double Sampler (CDS)
6 dB to 42 dB 10-Bit Variable Gain Amplifier (VGA)
12-Bit 36 MHz A/D Converter
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Generator
Precision Timing Core with <600 ps Resolution
On-Chip 3 V Horizontal and RG Drivers
2-Phase and 4-Phase H-Clock Modes
Electronic and Mechanical Shutter Modes
On-Chip Driver for External Crystal
On-Chip Sync Generator with External Sync Input
56-Lead LFCSP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
GENERAL DESCRIPTION
The AD9995 is a highly integrated CCD signal processor for
digital still camera and camcorder applications. It includes a
complete analog front end with A/D conversion, combined with a
full-function programmable timing generator. The timing genera-
tor is capable of supporting both 4- and 6-phase vertical clocking.
A Precision Timing core allows adjustment of high speed clocks
with less than 600 ps resolution at 36 MHz operation.
The AD9995 is specified at pixel rates of up to 36 MHz. The
analog front end includes black level clamping, CDS, VGA,
and a 12-bit A/D converter. The timing generator provides all
the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control. Operation is
programmed using a 3-wire serial interface.
Packaged in a space-saving 56-lead LFCSP, the AD9995 is speci-
fied over an operating temperature range of –20°C to +85°C.
CCDIN
FUNCTIONAL BLOCK DIAGRAM
VRT VRB
CDS
6dB TO 42dB
VGA
VREF
AD9995
12-BIT
ADC
12
DOUT
RG
H1–H4
V1–V6
VSG1–VSG5
HORIZONTAL
4 DRIVERS
6
V-H
5 CONTROL
INTERNAL CLOCKS
CLAMP
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
DCLK
MSHUT
STROBE
VSUB SUBCK
HD VD SYNC CLI CLO SL SCK DATA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.






AD9995 Datasheet, Funktion
AD9995
PIN CONFIGURATION
D5 1
D6 2
D7 3
D8 4
D9 5
D10 6
(MSB) D11 7
DRVDD 8
DRVSS 9
VSUB 10
SUBCK 11
V1 12
V2 13
V3 14
PIN 1
IDENTIFIER
AD9995
TOP VIEW
42 SDI
41 SL
40 REFB
39 REFT
38 AVSS
37 CCDIN
36 AVDD
35 CLI
34 CLO
33 TCVDD
32 TCVSS
31 RGVDD
30 RG
29 RGVSS
PIN FUNCTION DESCRIPTIONS1
Pin Mnemonic Type2 Description
Pin Mnemonic Type2 Description
1 D5
2 D6
3 D7
4 D8
5 D9
6 D10
7 D11
8 DRVDD
9 DRVSS
10 VSUB
11 SUBCK
12 V1
13 V2
14 V3
15 V4
16 V5
17 V6
18 VSG1
19 VSG2
20 VSG3
21 VSG4
22 VSG5
23 H1
24 H2
25 HVSS
26 HVDD
27 H3
28 H4
29 RGVSS
30 RG
31 RGVDD
32 TCVSS
33 TCVDD
34 CLO
35 CLI
DO Data Output
36 AVDD
P Analog Supply for AFE
DO Data Output
37 CCDIN
AI CCD Signal Input
DO Data Output
38 AVSS
P Analog Ground for AFE
DO Data Output
39 REFT
AO Voltage Reference Top Bypass
DO Data Output
40 REFB
AO Voltage Reference Bottom Bypass
DO Data Output
41 SL
DI 3-Wire Serial Load Pulse
DO Data Output (MSB)
42 SDI
DI 3-Wire Serial Data Input
P Data Output Driver Supply
43 SCK
DI 3-Wire Serial Clock
P Data Output Driver Ground
44 MSHUT DO Mechanical Shutter Pulse
DO CCD Substrate Bias
45 STROBE DO Strobe Pulse
DO CCD Substrate Clock (E-Shutter) 46 SYNC
DI External System Sync Input
DO CCD Vertical Transfer Clock 1
47 VD
DIO Vertical Sync Pulse
DO CCD Vertical Transfer Clock 2
(Input for Slave Mode,
DO CCD Vertical Transfer Clock 3
Output for Master Mode)
DO CCD Vertical Transfer Clock 4
48 DVSS
P Digital Ground
DO CCD Vertical Transfer Clock 5
49 DVDD
P Power Supply for VSG, V1–V6,
DO CCD Vertical Transfer Clock 6
HD/VD, MSHUT, STROBE,
DO CCD Sensor Gate Pulse 1
SYNC, and Serial Interface
DO CCD Sensor Gate Pulse 2
50 HD
DIO Horizontal Sync Pulse
DO CCD Sensor Gate Pulse 3
(Input for Slave Mode, Output for
DO CCD Sensor Gate Pulse 4
Master Mode)
DO CCD Sensor Gate Pulse 5
51 DCLK
DO Data Clock Output
DO CCD Horizontal Clock 1
52 D0
DO Data Output (LSB)
DO CCD Horizontal Clock 2
53 D1
DO Data Output
P H1–H4 Driver Ground
54 D2
DO Data Output
P H1–H4 Driver Supply
55 D3
DO Data Output
DO CCD Horizontal Clock 3
56 D4
DO Data Output
DO CCD Horizontal Clock 4
P RG Driver Ground
NOTES
1See Figure 38 for circuit configuration.
DO CCD Reset Gate Clock
P RG Driver Supply
2AI = Analog Input, AO = Analog Output, DI = Digital Input,
DO = Digital Output, DIO = Digital Input/Output, P = Power.
P Analog Ground for Timing Core
P Analog Supply for Timing Core
DO Clock Output for Crystal
DI Reference Clock Input
–6– REV. 0

6 Page









AD9995 pdf, datenblatt
AD9995
POSITION
PIXEL
PERIOD
RG
H1/H3
P[0]
RGr[0]
Hr[0]
P[12]
RGf[12]
P[24]
Hf[24]
P[36]
P[48] = P[0]
H2/H4
CCD
SIGNAL
SHP[24]
tS1
SHD[0]
NOTES
ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.
DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.
Figure 7. High SpeedTiming Default Locations
P[0]
PIXEL
PERIOD
P[12]
P[24]
P[36]
P[48] = P[0]
DCLK
DOUT
tOD
NOTES
DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.
OUTPUT DELAY (tOD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.
Figure 8a. Digital Output Phase Adjustment
CLI
CCDIN
SHD
(INTERNAL)
tCLIDLY
N–1
N
N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13
SAMPLE PIXEL N
DCLK
DOUT
N–13 N–12 N–11 N–10 N–9
PIPELINE LATENCY=11 CYCLES
N–8 N–7 N–6 N–5 N–4
N–3 N–2
N–1
N
N+1
NOTES
DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0, DCLKMODE = 0.
HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
Figure 8b. Pipeline Delay
–12–
N+2
REV. 0

12 Page





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