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PDF AD9954 Data sheet ( Hoja de datos )
| Número de pieza | AD9954 | |
| Descripción | 400 MSPS 14-Bit/ 1.8 V CMOS Direct Digital Synthesizer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9954 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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400 MSPS 14-Bit, 1.8 V CMOS
Direct Digital Synthesizer
AD9954
FEATURES
400 MSPS internal clock speed
Integrated 14-bit DAC
Programmable phase/amplitude dithering
32-bit tuning word
Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)
Excellent dynamic performance
>80 dB SFDR @ 160 MHz (±100 kHz offset) AOUT
Serial I/O control
Ultrahigh speed analog comparator
Automatic linear and nonlinear frequency sweeping
capability
4 frequency/phase offset profiles
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP/EP package
Integrated 1024 word × 32-bit RAM
Support for 5 V input levels on most digital inputs
PLL REFCLK multiplier (4× to 20×)
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Multichip synchronization
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Automotive radar
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
FREQUENCY
ACCUMULATOR 32
STATIC RAM
1024 × 32
RAM
DATA
32
M
U
X
32
DDS CORE
PHASE
ACCUMULATOR
Z–1
32
PHASE
OFFSET
19
COS(X)
AD9954
14 DAC
I/O UPDATE
SYNC_CLK
REFCLK
REFCLK
14
Z–1
32 3
10
0
M
U
X
DDS
32 CLOCK
MUX
RAM DATA 14
<31:18>
θ
TIMING AND CONTROL LOGIC
SYNC
÷4
CONTROL REGISTERS
OSCILLATOR/BUFFER
ENABLE
4×–20×
CLOCK
MULTIPLIER
M
U SYSTEM
X CLOCK
SYSTEM
14 CLOCK
COMPARATOR
DAC_RSET
IOUT
IOUT
SYNC_IN
OSK
PWRDWNCTL
COMP_IN
COMP_IN
COMP_OUT
CRYSTAL OUT
PS<1:0> I/O PORT
Figure 1. 48-LeadTQFP/EP
RESET
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
Parameter
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance
Input Resistance
Input Current
Hysteresis
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage, High Z Load
Logic 0 Voltage, High Z Load
Propagation Delay
Output Duty Cycle Error
Rise/Fall Time, 5 pF Load
Toggle Rate, High Z Load
Output Jitter2
COMPARATOR NARROWBAND SFDR
10 MHz (1 MHz)
10 MHz (250 kHz)
10 MHz (50 kHz)
10 MHz (10 kHz)
70 MHz (1 MHz)
70 MHz (250 kHz)
70 MHz (50 kHz)
70 MHz (10 kHz)
110 MHz (1 MHz)
110 MHz (250 kHz)
110 MHz (50 kHz)
110 MHz (10 kHz)
140 MHz (1 MHz)
140 MHz (250 kHz)
140 MHz (50 kHz)
140 MHz (10 kHz)
160 MHz (1 MHz)
160 MHz (250 kHz)
160 MHz (50 kHz)
160 MHz (10 kHz)
CLOCK GENERATOR OUTPUT JITTER3
5 MHz AOUT
10 MHz AOUT
40 MHz AOUT
80 MHz AOUT
120 MHz AOUT
140 MHz AOUT
160 MHz AOUT
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Minimum Clock Pulse Width Low
Minimum Clock Pulse Width High
Maximum Clock Rise/Fall Time
Minimum Data Setup Time DVDD_I/O = 3.3 V
Minimum Data Setup Time DVDD_I/O = 1.8 V
Minimum Data Hold Time
Test
Temp Level Min
25°C V
25°C IV
25°C I
25°C IV
30
FULL
FULL
25°C
25°C
25°C
25°C
25°C
VI
VI
IV
IV
IV
IV
IV
1.6
200
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
IV
IV
IV
IV
IV
IV
IV
IV
7
7
3
5
0
Rev. 0 | Page 5 of 36
Typ Max
3
500
±12
45
0.4
3
±5
1
1
80
85
90
95
80
85
90
95
80
85
90
95
80
85
90
95
80
85
90
95
100
60
50
50
50
50
50
25
2
AD9954
Unit
pF
kΩ
µA
mV
V
V
ns
%
ns
MHz
ps RMS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
ps RMS
ps RMS
ps RMS
ps RMS
ps RMS
ps RMS
ps RMS
Mbps
ns
ns
ns
ns
ns
ns
5 Page 
REF –4dBm
PEAK 0
LOG
10dB/ –10
–20
ATTEN 10dB
1
–30
–40 MARKER
1.105000MHz
–50 –5.679dBm
–60
W1 S2
S3 FC –70
AA
–80
–90
ST
–100
CENTER 1.105MHz
#RES BW 30Hz
VBW 30Hz
MKR1 1.105MHz
–5.679dBm
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
Figure 10. FOUT = 1.1 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
REF 0dBm
PEAK 0
LOG
10dB/ –10
ATTEN 10dB
1R
MKR1 85kHz
–93.01dB
–20
–30
–40 MARKER
40.000000MHz
–50 –56.2dB
–60
W1 S2
S3 FC –70
AA
–80
–90
–100
CENTER 10MHz
#RES BW 30Hz
1
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
Figure 11. FOUT = 10 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
REF 0dBm
PEAK 0
LOG
10dB/ –10
ATTEN 10dB
1
MKR1 39.905MHz
–5.347dBm
–20
–30
–40 MARKER
39.905000MHz
–50 –5.347dBm
–60
W1 S2
S3 FC –70
AA
–80
–90
–100
CENTER 39.9MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
Figure 12. FOUT = 39.9 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
AD9954
REF –4dBm
PEAK 0
LOG
10dB/ –10
–20
ATTEN 10dB
1
–30
–40 MARKER
80.301000MHz
–50 –6.318dBm
–60
W1 S2
S3 FC –70
AA
–80
–90
ST
–100
CENTER 80.25MHz
#RES BW 30Hz
VBW 30Hz
MKR1 80.301MHz
–6.318dBm
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
Figure 13. FOUT = 80.3 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
REF –4dBm
PEAK 0
LOG
10dB/ –10
ATTEN 10dB
1
MKR1 120.205MHz
–6.825dBm
–20
–30
–40 MARKER
120.205000MHz
–50 –6.825dBm
–60
W1 S2
S3 FC –70
AA
–80
–90
ST
–100
CENTER 120.2MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
Figure 14. FOUT = 120.2 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
REF –4dBm
PEAK 0
LOG
10dB/ –10
ATTEN 10dB
1
MKR1 600kHz
–0.911dB
–20
–30
–40 CENTER
160.5000000MHz
–50
–60
W1 S2
S3 FC –70
AA
–80
–90
ST
–100
CENTER 160.5MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
Figure 15. FOUT = 160 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
Rev. 0 | Page 11 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9954.PDF ] | |
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