|
|
PDF AD9952 Data sheet ( Hoja de datos )
| Número de pieza | AD9952 | |
| Descripción | Direct Digital Synthesizer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9952 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
400 MSPS 14-Bit, 1.8 V CMOS
Direct Digital Synthesizer
AD9952
FEATURES
400 MSPS internal clock speed
Integrated 14-bit DAC
32-bit tuning word
Phase noise ≤ −120 dBc/Hz @ 1 kHz offset (DAC output)
Excellent dynamic performance
>80 dB SFDR @ 160 MHz (±100 kHz offset) AOUT
Serial I/O control
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP_EP package
Support for 5 V input levels on most digital inputs
PLL REFCLK multiplier (4× to 20×)
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Multichip synchronization
High speed comparator (200 MHz toggle rate)
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generators
Test and measurement equipment
Acousto-optic device drivers
GENERAL DESCRIPTION
The AD9952 is a direct digital synthesizer (DDS) featuring a
14-bit DAC (digital-to-analog converter) and operating up to
400 MSPS. The AD9952 uses advanced DDS technology,
coupled with an internal high speed, high performance DAC to
form a digitally programmable, complete high frequency
synthesizer capable of generating a frequency-agile analog
output sinusoidal waveform at up to 200 MHz. The AD9952 is
designed to provide fast frequency hopping and fine tuning
resolution (32-bit frequency tuning word). The frequency
tuning and control words are loaded into the AD9952 via a
serial I/O port.
The AD9952 is specified to operate over the extended industrial
temperature range of −40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
DDS CORE
PHASE
ACCUMULATOR
Z–1
32
PHASE
OFFSET
19
COS(X)
AD9952
14 DAC
14
SYSTEM
CLOCK
Z–1
DAC_RSET
IOUT
IOUT
32 14
I/O UPDATE
SYNC_CLK
REFCLK
REFCLK
0
M
U
X
SYNC
OSCILLATOR/BUFFER
ENABLE
4× TO 20×
CLOCK
MULTIPLIER
TIMING AND CONTROL LOGIC
÷ 4 CONTROL REGISTERS
M
U SYSTEM
X CLOCK
SYNC_IN
OSK
PWRDWNCTL
COMPARATOR
COMP_IN
COMP_IN
COMP_OUT
CRYSTAL OUT
I/O PORT
Figure 1.
RESET
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.
1 page  
AD9952
ELECTRICAL SPECIFICATIONS
AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, DAC_RSET = 3.92 kΩ, external reference clock frequency = 400 MHz with
REFCLK multiplier disabled, unless otherwise noted. DAC output must be referenced to AVDD, not AGND.
Table 1.
Parameter
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Disabled
REFCLK Multiplier Enabled @ 4×
REFCLK Multiplier Enabled @ 20×
Input Capacitance
Input Impedance
Duty Cycle
Duty Cycle with REFCLK Multiplier Enabled
REFCLK Input Power1
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Residual Phase Noise @ 1 kHz Offset, 40 MHz AOUT
REFCLK Multiplier Enabled @ 20×
REFCLK Multiplier Enabled @ 4×
REFCLK Multiplier Disabled
Voltage Compliance Range
Wideband Spurious-Free Dynamic Range (SFDR)
1 MHz to 10 MHz Analog Out
10 MHz to 40 MHz Analog Out
40 MHz to 80 MHz Analog Out
80 MHz to 120 MHz Analog Out
120 MHz to 160 MHz Analog Out
Narrow-Band SFDR
40 MHz Analog Out (±1 MHz)
40 MHz Analog Out (±250 kHz)
40 MHz Analog Out (±50 kHz)
40 MHz Analog Out (±10 kHz)
80 MHz Analog Out (±1 MHz)
80 MHz Analog Out (±250 kHz)
80 MHz Analog Out (±50 kHz)
80 MHz Analog Out (±10 kHz)
120 MHz Analog Out (±1 MHz)
120 MHz Analog Out (±250 kHz)
120 MHz Analog Out (±50 kHz)
120 MHz Analog Out (±10 kHz)
160 MHz Analog Out (±1 MHz)
160 MHz Analog Out (±250 kHz)
160 MHz Analog Out (±50 kHz)
160 MHz Analog Out (±10 kHz)
Temp Min
Typ Max
Unit
Full 1
Full 20
Full 4
25°C
25°C
25°C
25°C 35
Full –15
25°C 5
25°C –10
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C AVDD −
0.5
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
400
100
20
3
1.5
50
65
0 +3
MHz
MHz
MHz
pF
kΩ
%
%
dBm
14
10 15
+10
0.6
1
2
5
Bits
mA
%FS
µA
LSB
LSB
pF
–105
–115
–132
AVDD + 0.5
dBc/Hz
dBc/Hz
dBc/Hz
V
73 dBc
67 dBc
62 dBc
58 dBc
52 dBc
87 dBc
89 dBc
91 dBc
93 dBc
85 dBc
87 dBc
89 dBc
91 dBc
83 dBc
85 dBc
87 dBc
89 dBc
81 dBc
83 dBc
85 dBc
87 dBc
Rev. B | Page 3 of 28
5 Page 
TYPICAL PERFORMANCE CHARACTERISTICS
REF 0dBm
PEAK 0
LOG
1R
10dB/ –10
–20
ATTEN 10dB
MKR1 98.0MHz
–70.68dB
–30
–40 MARKER
100.000000MHz
–50 –70.68dB
–60
W1 S2
S3 FC –70
AA
–80
1
–90
–100
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
Figure 3. FOUT = 1 MHz
FCLK = 400 MSPS, WBSFDR
REF 0dBm
PEAK 0
LOG
10dB/ –10
1R
–20
ATTEN 10dB
MKR1 80.0MHz
–69.12dB
–30
–40 MARKER
80.000000MHz
–50 –69.12dB
–60
W1 S2
S3 FC –70
AA
–80
1
–90
–100
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
Figure 4. FOUT = 10 MHz, FCLK = 400 MSPS, WBSFDR
REF 0dBm
PEAK 0
LOG
10dB/ –10
–20
ATTEN 10dB
1R
MKR1 0Hz
–68.44dB
–30
–40 MARKER
40.000000MHz
–50 –68.44dB
–60
W1 S2
S3 FC –70
AA
–80
1
–90
–100
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
Figure 5. FOUT = 40 MHz, FCLK = 400 MSPS, WBSFDR
AD9952
REF 0dBm
PEAK 0
LOG
10dB/ –10
–20
ATTEN 10dB
1R
MKR1 80.0MHz
–61.55dB
–30
–40 MARKER
80.000000MHz
–50 –61.55dB
–60
W1 S2
S3 FC –70
AA
–80
1
–90
–100
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
Figure 6. FOUT = 80 MHz
FCLK = 400 MSPS, WBSFDR
REF 0dBm
PEAK 0
LOG
10dB/ –10
–20
ATTEN 10dB
MKR1 40.0MHz
–56.2dB
1R
–30
–40
–50
–60
W1 S2
S3 FC –70
AA
–80
MARKER
40.000000MHz
–56.2dB
1
–90
–100
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
Figure 7. FOUT = 120 MHz, FCLK = 400 MSPS, WBSFDR
REF 0dBm
PEAK 0
LOG
10dB/ –10
–20
ATTEN 10dB
MKR1 0Hz
–53.17dB
1R
–30
–40
–50
–60
W1 S2
S3 FC –70
AA
–80
MARKER
80.000000MHz
–53.17dB
1
–90
–100
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
Figure 8. FOUT = 160 MHz, FCLK = 400 MSPS, WBSFDR
Rev. B | Page 9 of 28
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9952.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9951 | CMOS Direct Digital Synthesize | Analog Devices |
| AD9952 | Direct Digital Synthesizer | Analog Devices |
| AD9953 | 1.8V CMOS Direct Digital Synthesizer | Analog Devices |
| AD9954 | 400 MSPS 14-Bit/ 1.8 V CMOS Direct Digital Synthesizer | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |