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PDF AD9937 Data sheet ( Hoja de datos )
| Número de pieza | AD9937 | |
| Descripción | CCD Signal Processor with Precision Timing Generator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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CCD Signal Processor with
Precision Timing™ Generator
AD9937
FEATURES
12 MSPS Correlated Double Sampler (CDS)
10-Bit 12 MHz A/D Converter
No Missing Codes Guaranteed
6 dB to 40 dB Variable Gain Amplifier (VGA)
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Generator
Precision Timing Core with 1.7 ns Resolution
On-Chip: 6-Channel Horizontal and 1-Channel RS Drivers
4-Phase Vertical Transfer Clocks
Electronic and Mechanical Shutter Modes
On-Chip Sync Generator with External Sync Option
APPLICATIONS
Digital Still Cameras
Industrial Imaging
GENERAL DESCRIPTION
The AD9937 is a highly integrated CCD signal processor. It
includes a complete analog front end with A/D conversion,
combined with a full-function programmable timing generator.
A Precision Timing core allows adjustment of high speed clocks
with 1.7 ns resolution at 12 MHz operation.
The AD9937 is specified at pixel rates of up to 12 MHz. The
analog front end includes black level clamping, CDS, VGA, and
a 10-bit A/D converter. The timing generator provides all the
necessary CCD clocks: RS, H-clocks, V-clocks, sensor gate pulses,
and substrate charge reset pulse. Operation is programmed using a
3-wire serial interface.
The AD9937 is packaged in a 56-lead LFCSP and specified over
an operating temperature range of –25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9937
6dB TO 40dB
CDS
VGA
VREF
ADC
10
DOUT
RS
H1 A–D
H2 A, B
V1 A/B
V2
V3 A/B
V4
TG1A
TG1B
TG3A
TG3B
HORIZONTAL
6 DRIVERS
4
V-H
CONTROL
4
CLAMP
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
VCLK
LM OFD
HD VD
VCKM SLD SCK SDA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
AD9937
TIMING SPECIFICATIONS (CL = 20 pF, AVDD = DVDD = DRVDD = 3 V, fCLI = 12 MHz, unless otherwise noted.)
Parameter
Symbol
Min Typ Max
MASTER CLOCK, VCKM
VCKM Clock Period
VCKM High/Low Pulsewidth
Delay from VCKM Rising Edge to Internal Pixel Position 0
AFE CLAMP PULSES1
CLPOB Pulsewidth2
tCONV
tVCKMDLY
83.33
2
41.67
9
20
AFE SAMPLE LOCATION1 (See Figure 13)
SHP Sample Edge to SHD Sample Edge
tS1
33.34
41.67
DATA OUTPUTS
Output Delay from VCLK Rising Edge
Pipeline Delay from SHP/SHD Sampling (See Figure 40)
tOD
9
9
SERIAL INTERFACE
Maximum SCK Frequency
SLD to SCK Setup Time
SCK to SLD Hold Time
SDA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDA Valid Hold
SCK Falling Edge to SDA Valid Read
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
NOTES
1Parameter is programmable.
2Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Specifications subject to change without notice.
Unit
ns
ns
ns
Pixels
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns
ABSOLUTE MAXIMUM RATINGS
Parameter
With
Respect
To Min Max
Unit
AVDD
AVSS –0.3 +3.9
V
TCVDD
TCVSS –0.3 +3.9
V
HVDD
HVSS –0.3 +3.9
V
RSVDD
RSVSS –0.3 +3.9
V
DVDD
DVSS –0.3 +3.9
V
DRVDD
DRVSS –0.3 +3.9
V
RS Output
RSVSS –0.3 RSVDD + 0.3 V
H1(A–D), H2(A, B)Output HVSS –0.3 HVDD + 0.3 V
Digital Outputs
DVSS –0.3 DVDD + 0.3 V
Digital Inputs
DVSS –0.3 DVDD + 0.3 V
SCK, SLD, SDA
DVSS –0.3 DVDD + 0.3 V
VRT, VRB
AVSS –0.3 AVDD + 0.3 V
CCDIN
AVSS –0.3 AVDD + 0.3 V
Junction Temperature
150 °C
Lead Temperature, 10 sec
350 °C
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
JA = 24.9°C/W
ORDERING GUIDE
Model
AD9937KCP
Temperature
Range
–25°C to +85°C
AD9937KCPRL –25°C to +85°C
Package
Description
Lead Frame
Chip Scale
Package
(LFCSP)
Lead Frame
Chip Scale
Package
(LFCSP)
Package
Option
CP-56
CP-56
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9937 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–5–
5 Page 
AD9937
Table II. VTP Sequence System Register Map (Addr 0x14) (continued)
Addr
Bit Bit
Breakdown Width
VTP_Reg(6)
(8:0)
(17:9)
(26:18)
(31:27)
9
9
9
5
VTP_Reg(7)
(8:0)
(17:9)
(26:18)
27
28
29
30
31
9
9
9
1
1
1
1
1
VTP_Reg(8)
(8:0)
(17:9)
(26:18)
(31:27)
9
9
9
5
VTP_Reg(9)
(8:0)
(17:9)
(26:18)
(31:27)
9
9
9
5
VTP_Reg(10) (11:0)
(23:12)
(31:24)
12
12
8
VTP_Reg(11) (11:0)
(23:12)
(31:24)
12
12
8
VTP_Reg(12) (11:0)
(23:12)
(31:24)
12
12
8
VTP_Reg(13) (11:0)
(23:12)
(31:24)
12
12
8
Default
85
1
71
99
29
99
1
0
0
1
15
57
43
85
1
71
40
410
490
780
80
360
450
820
Register
Name
V3TOG2_1
V4TOG1_1
V4TOG2_1
Unused
VTPLEN_2
V1TOG1_2
V1TOG2_2
V1POL_2
V2POL_2
V3POL_2
V4POL_2
Unused
V2TOG1_2
V2TOG2_2
V3TOG1_2
Unused
V3TOG2_2
V4TOG1_2
V4TOG2_2
Unused
SP1TOG1
SP1TOG2
Unused
SP2TOG1
SP2TOG2
Unused
SP3TOG1
SP3TOG2
Unused
SP4TOG1
SP4TOG2
Unused
Function
VTP1: V3 Toggle Position 2
VTP1: V4 Toggle Position 1
VTP1: V4 Toggle Position 2
VTP2: Length between Repetitions
VTP2: V1 Toggle Position 1
VTP2: V1 Toggle Position 2
VTP2: V1 Start Polarity
VTP2: V2 Start Polarity
VTP2: V3 Start Polarity
VTP2: V4 Start Polarity
VTP2: V2 Toggle Position 1
VTP2: V2 Toggle Position 2
VTP2: V3 Toggle Position 1
VTP2: V3 Toggle Position 2
VTP2: V4 Toggle Position 1
VTP2: V4 Toggle Position 2
SP1 Toggle Position 1 (V1A/V1B)
SP1 Toggle Position 2 (V1A/V1B)
SP2 Toggle Position 1 (V2)
SP2 Toggle Position 2 (V2)
SP3 Toggle Position 1 (V3A/V3B)
SP3 Toggle Position 2 (V3A/V3B)
SP4 Toggle Position 1 (V4)
SP4 Toggle Position 2 (V4)
REV. 0
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9937.PDF ] | |
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