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AD9901 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9901
Beschreibung Ultrahigh Speed Phase/Frequency Discriminator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 8 Seiten
AD9901 Datasheet, Funktion
a
FEATURES
Phase and Frequency Detection
ECL/TTL/CMOS Compatible
Linear Transfer Function
No “Dead Zone”
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Low Phase Noise Reference Loops
Fast-Tuning “Agile” IF Loops
Secure “Hopping” Communications
Coherent Radar Transmitter/Receiver Chains
Ultrahigh Speed
Phase/Frequency Discriminator
AD9901
PHASE-LOCKED LOOP
REFERENCE
INPUT
AD9901
LOW-
PASS
FILTER
VCO
OSCILLATOR
OUTPUT
1/N
OPTIONAL 1/N PRESCALER
TYPICAL OF DIGITAL PLLs
GENERAL DESCRIPTION
The AD9901 is a digital phase/frequency discriminator capable
of directly comparing phase/frequency inputs up to 200 MHz.
Processing in a high speed trench-oxide isolated process, com-
bined with an innovative design, gives the AD9901 a linear
detection range, free of indeterminate phase detection zones
common to other digital designs.
With a single +5 V supply, the AD9901 can be configured to
operate with TTL or CMOS logic levels; it can also operate
with ECL inputs when operated with a –5.2 V supply. The
open-collector outputs allow the output swing to be matched to
post-filtering input requirements. A simple current setting resis-
tor controls the output stage current range, permitting a reduc-
tion in power when operated at lower frequencies.
A major feature of the AD9901 is its ability to compare
phase/frequency inputs at standard IF frequencies without
prescalers. Excessive phase uncertainty which is common with
standard PLL configurations is also eliminated. The AD9901
provides the locking speed of traditional phase/frequency dis-
criminators, with the phase stability of analog mixers.
The AD9901 is available as a commercial temperature range
device, 0°C to +70°C, and as a military temperature device,
–55°C to +125°C. The commercial versions are packaged in a
14-lead ceramic DIP and a 20-lead PLCC.
The AD9901 Phase/Frequency Discriminator is available in
versions compliant with MIL-STD-883. Refer to the Analog
Devices Military Products Databook or current AD9901/883B
data sheet for specifications.
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
INPUT
OSCILLATOR
INPUT
DQ
REFERENCE
INPUT
FLIP-FLOP
Q
DQ
OSCILLATOR
INPUT
FLIP-FLOP
Q
XOR
DQ
REFERENCE
FREQUENCY
DISCRIMINATOR
FLIP-FLOP
RQ
DS
Q
OSCILLATOR
FREQUENCY
DISCRIMINATOR
FLIP-FLOP
Q
OUTPUT
OUTPUT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999






AD9901 Datasheet, Funktion
AD9901
THEORY OF OPERATION
A phase detector is one of three basic components of a phase-
locked loop (PLL); the other two are a filter and a tunable oscil-
lator. A basic PLL control system is shown in Figure 3.
REFERENCE
INPUT
AD9901
LOW-
PASS
FILTER
VCO
OSCILLATOR
OUTPUT
1/N
OPTIONAL 1/N PRESCALER
TYPICAL OF DIGITAL PLLs
Figure 3. Phase-Locked Loop Control System
The function of the phase detector is to generate an error signal
that is used to retune the oscillator frequency whenever its out-
put deviates from a reference input signal. The two most com-
mon methods of implementing phase detectors are (1) an analog
mixer and (2) a family of sequential logic circuits known as
digital phase detectors.
The AD9901 is a digital phase detector. As illustrated in the
block diagram of the unit, straightforward sequential logic de-
sign is used. The main components include four “D” flip-flops,
an exclusive-OR gate (XOR) and some combinational output
logic. The circuit operates in two distinct modes: as a linear
phase detector and as a frequency discriminator.
When the reference and oscillator are very close in frequency,
only the phase detection circuit is active. If the two inputs are
substantially different in frequency, the frequency discrimina-
tion circuit overrides the phase detector portion to drive the
oscillator frequency toward the reference frequency and put it
within range of the phase detector.
Input signals to the AD9901 are pulse trains, and its output
duty cycle is proportional to the phase difference of the oscilla-
tor and reference inputs. Figures 4, 5 and 6 illustrate, respec-
tively, the input/output relationships at lock; with the
REFERENCE
INPUT
REFERENCE
INPUT
OSCILLATOR
INPUT
REFERENCE
FLIP-FLOP
OUTPUT
OSCILLATOR
FLIP-FLOP
OUTPUT
XORGATE
OUTPUT
DC MEAN VALUE
Figure 6. Timing Waveforms (φOUT Lags φIN)
oscillator leading the reference frequency; and with the oscillator
lagging. This output pulse train is low-pass filtered to extract the
dc mean value [Kφ (φI φO)] where Kφ is a proportionality con-
stant (phase gain).
At or near lock (Figures 4, 5 and 6), only the two input flip-
flops and the exclusive-OR gate (the phase detection circuit) are
active. The input flip-flops divide both the reference and oscilla-
tor frequencies by a factor of two. This insures that inputs to the
exclusive-OR are square waves, regardless of the input duty
cycles of the frequencies being compared. This division-by-two
also moves the nonlinear detection range to the ends of the
range rather than near lock, which is the case with conventional
digital phase detectors.
Figure 7 illustrates the constant gain near lock.
2
FO = 70MHz
FO = 200MHz
FO = 50MHz
1
TYPICAL PHASE DETECTOR
GAIN IS 0.2865V/RAD
VOUT = 1.8V
OSCILLATOR
INPUT
REFERENCE
FLIP-FLOP
OUTPUT
OSCILLATOR
FLIP-FLOP
OUTPUT
XORGATE
OUTPUT
DC MEAN VALUE
Figure 4. AD9901 Timing Waveforms at “Lock”
REFERENCE
INPUT
OSCILLATOR
INPUT
REFERENCE
FLIP-FLOP
OUTPUT
OSCILLATOR
FLIP-FLOP
OUTPUT
XORGATE
OUTPUT
DC MEAN VALUE
Figure 5. Timing Waveforms (φOUT Leads φIN)
0
–2
PHASE DIFFERENCE AT INPUTS
0
Figure 7. Phase Gain Plot
When the two square waves are combined by the XOR, the
output has a 50% duty cycle if the reference and oscillator in-
puts are exactly 180° out of phase; under these conditions, the
AD9901 is operating in a locked mode. Any shift in the phase
relationship between these input signals causes a change in the
output duty cycle. Near lock, the frequency discriminator flip-
flops provide constant HIGH levels to gate the XOR output to
the final output.
The duty cycle of the AD9901 is a direct measure of the phase
difference between the two input signals when the unit is near
lock. The transfer function can be stated as [Kφ(φI φO](V/RAD),
where Kφ is the allowable output voltage range of the AD9901
divided by 2 π.
For a typical output swing of 1.8 V, the transfer function can be
stated as (1.8 V/2 π = 0.285 V/RAD). Figure 7 shows the rela-
tionship of the dc mean value of the AD9901 output as a func-
tion of the phase difference of the two inputs.
–6– REV. B

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