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AD9891 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9891
Beschreibung CCD Signal Processors with Precision Timing Generator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 59 Seiten
AD9891 Datasheet, Funktion
a
CCD Signal Processors with
Precision TimingGenerator
AD9891/AD9895
FEATURES
AD9891: 10-Bit 20 MHz Version
AD9895: 12-Bit 30 MHz Version
Correlated Double Sampler (CDS)
4 ؎6 dB Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 20 MHz A/D Converter (AD9891)
12-Bit 30 MHz A/D Converter (AD9895)
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Generator
Precision Timing Core with 1 ns Resolution
On-Chip 5 V Horizontal and RG Drivers
2-Phase and 4-Phase H-Clock Modes
4-Phase Vertical Transfer Clocks
Electronic and Mechanical Shutter Modes
On-Chip Driver for External Crystal
On-Chip Sync Generator with External Sync Option
64-Lead CSPBGA Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
PRODUCT DESCRIPTION
The AD9891 and AD9895 are highly integrated CCD signal
processors for digital still camera applications. Both include a
complete analog front end with A/D conversion combined with
a full-function programmable timing generator. A Precision
Timing core allows adjustment of high speed clocks with 1 ns
resolution at 20 MHz operation and 700 ps resolution at 30
MHz operation.
The AD9891 is specified at pixel rates of up to 20 MHz, and
the AD9895 is specified at 30 MHz. The analog front end
includes black level clamping, CDS, PxGA, VGA, and a 10-Bit
or 12-Bit A/D converter. The timing generator provides all the
necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control. Operation is
programmed using a 3-wire serial interface.
Packaged in a space-saving 64-lead CSPBGA, the AD9891 and
AD9895 are specified over an operating temperature range of
20°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
CCDIN
CDS
VRT VRB
4dB ؎ 6dB
PxGA
2dB TO 36dB
VGA
VREF
AD9891/AD9895
ADC
10 OR 12
DOUT
CLAMP
RG
H1–H4
V1–V4
VSG1–VSG8
HORIZONTAL
4 DRIVERS
4
V-H
8 CONTROL
INTERNAL CLOCKS
CLAMP
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
DCLK
CLPOB/PBLK
FD/LD
MSHUT
STROBE
CLO
VSUB SUBCK
HD VD SYNC CLI
SL SCK DATA
PxGA is a registered trademark and Precision Timing is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002






AD9891 Datasheet, Funktion
AD9891/AD9895
TIMING SPECIFICATIONS (CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 20 MHz [AD9891] or 30 MHz [AD9895], unless
otherwise noted.)
Parameter
Symbol
Min Typ Max
Unit
MASTER CLOCK, CLI (Figure 7)
CLI Clock Period, AD9891
CLI High/Low Pulsewidth, AD9891
CLI Clock Period, AD9895
CLI High/Low Pulsewidth, AD9895
Delay from CLI Rising Edge to Internal Pixel Position 0
AFE CLAMP PULSES1 (Figure 13)
CLPDM Pulsewidth
CLPOB Pulsewidth2
AFE SAMPLE LOCATION1 (Figure 10)
SHP Sample Edge to SHD Sample Edge, AD9891
SHP Sample Edge to SHD Sample Edge, AD9895
DATA OUTPUTS (Figure 12)
Output Delay from DCLK Rising Edge1
Pipeline Delay from SHP/SHD Sampling
tCONV
tCONV
tCLIDLY
tS1
tS1
tOD
50
20 25
33.3
13 16.7
6
4 10
2 20
20 25
13 16.7
8
9
ns
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
Cycles
SERIAL INTERFACE (Figures 52 and 53)
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
NOTES
1Parameter is programmable.
2Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
MHz
ns
ns
ns
ns
ns
ABSOLUTE MAXIMUM RATINGS
Parameter
With
Respect
To Min Max
Unit
AVDD1, AVDD2
TCVDD
HVDD
RGVDD
DVDD
DRVDD
RG Output
H1H4 Output
Digital Outputs
Digital Inputs
SCK, SL, SDATA
VRT, VRB
BYP1BYP3, CCDIN
Junction Temperature
Lead Temperature, 10 sec
AVSS
TCVSS
HVSS
RGVSS
DVSS
DRVSS
RGVSS
HVSS
DVSS
DVSS
DVSS
AVSS
AVSS
0.3 +3.9
0.3 +3.9
0.3 +5.5
0.3 +5.5
0.3 +3.9
0.3 +3.9
0.3 RGVDD + 0.3
0.3 HVDD + 0.3
0.3 DVDD + 0.3
0.3 DVDD + 0.3
0.3 DVDD + 0.3
0.3 AVDD + 0.3
0.3 AVDD + 0.3
150
350
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
JA = 61°C/W
JC = 29.7°C/W
ORDERING GUIDE
Model
Temperature
Range
AD9891KBC 20°C to +85°C
AD9895KBC 20°C to +85°C
Package
Description
CSPBGA
CSPBGA
Package
Option
BC-64
BC-64
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9891 and AD9895 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6– REV. A

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AD9891 pdf, datenblatt
AD9891/AD9895
PRECISION TIMING HIGH SPEED TIMING GENERATION
The AD9891/AD9895 generates flexible, high speed timing
signals using the Precision Timing core. This core is the founda-
tion for generating the timing used for both the CCD and the
AFE: the reset gate RG, horizontal drivers H1H4, and the
SHP/SHD sample clocks. A unique architecture makes it rou-
tine for the system designer to optimize image quality by
providing precise control over the horizontal CCD readout and
the AFE correlated double sampling.
The high speed timing of the AD9891/AD9895 operates the
same in either Master or Slave Mode configuration.
Timing Resolution
The Precision Timing core uses a 1ϫ master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 7 illustrates how the internal timing
core divides the master clock period into 48 steps or edge posi-
tions. Using a 20 MHz CLI frequency, the edge resolution of
the Precision Timing core is 1 ns. If a 1ϫ system clock is not
available, it is also possible to use a 2ϫ reference clock by pro-
gramming the CLIDIVIDE Register (Addr x01F). The AD9891/
AD9895 will then internally divide the CLI frequency by two.
The AD9891/AD9895 also includes a master clock output,
CLO, which is the inverse of CLI. This output is intended to be
used as a crystal driver. A crystal can be placed between the
CLI and CLO Pins to generate the master clock for the
AD9891/AD9895. For more information on using a crystal, see
Figure 51.
High Speed Clock Programmability
Figure 8 shows how the high speed clocks RG, H1H4, SHP,
and SHD are generated. The RG pulse has programmable
rising and falling edges, and may be inverted using the polarity
control. The horizontal clocks H1 and H3 have programmable
rising and falling edges and polarity control. The H2 and H4
clocks are always inverses of H1 and H3, respectively.
Table I summarizes the high speed timing registers and their
parameters. Figure 9 shows the typical 2-phase H-clock
arrangement in which H3 and H4 are programmed for the same
edge location as H1 and H2.
The edge location registers are six bits wide, but there are only
48 valid edge locations available. Therefore, the register values
are mapped into four quadrants, with each quadrant containing
12 edge locations. Table II shows the correct register values for
POSITION
CLI
tCLIDLY
1 PIXEL
PERIOD
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
NOTES
PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6ns TYP).
Figure 7. High Speed Clock Resolution from CLI Master Clock Input
CCD
SIGNAL
1
RG
5
H1
3
2
6
4
H2
7
H3
8
H4
PROGRAMMABLE CLOCK POSITIONS:
1: RG RISING EDGE
2: RG FALLING EDGE
3: SHP SAMPLE LOCATION
4: SHD SAMPLE LOCATION
5: H1 RISING EDGE POSITION AND 6: H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1)
7: H3 RISING EDGE POSITION AND 8: H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3)
Figure 8. High Speed Clock Programmable Locations
–12–
REV. A

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