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AD9884A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9884A
Beschreibung 100 MSPS/140 MSPS Analog Flat Panel Interface
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
AD9884A Datasheet, Funktion
a
FEATURES
140 MSPS Maximum Conversion Rate
500 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
400 ps p-p PLL Clock Jitter
Power-Down Mode
3.3 V Power Supply
2.5 V to 3.3 V Three-State CMOS Outputs
Demultiplexed Output Ports
Data Clock Output Provided
Low Power: 570 mW Typical
Internal PLL Generates CLOCK from HSYNC
Serial Port Interface
Fully Programmable
Supports Alternate Pixel Sampling for Higher-
Resolution Applications
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
100 MSPS/140 MSPS
Analog Flat Panel Interface
AD9884A
FUNCTIONAL BLOCK DIAGRAM
RIN CLAMP
GIN CLAMP
BIN CLAMP
HSYNC
COAST
CLAMP
CKINV
CKEXT
CLOCK
GENERATOR
0.15V
8
A/D
8
A/D
8
A/D
2
AD9884A
8
8
ROUTA
ROUTB
8
GOUTA
8
GOUTB
8
BOUTA
8
BOUTB
DATACK
HSOUT
CONTROL
REF
REFIN
FILT SOGIN SOGOUT SDA SCL A0 A1 PWRDN REFOUT
GENERAL DESCRIPTION
The AD9884A is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full-power analog bandwidth of 500 MHz
supports display resolutions of up to 1280 × 1024 (SXGA) at
75 Hz with sufficient input bandwidth to accurately acquire and
digitize each pixel.
To minimize system cost and power dissipation, the AD9884A
includes an internal 1.25 V reference, PLL to generate a pixel
clock from HSYNC, and programmable gain, offset and clamp
circuits. The user provides only a 3.3 V power supply, analog
input, and HSYNC signals. Three-state CMOS outputs may be
powered by a supply between 2.5 V and 3.3 V.
The AD9884A’s on-chip PLL generates a pixel clock from the
HSYNC input. Pixel clock output frequencies range from
20 MHz to 140 MHz. PLL clock jitter is typically 400 ps p-p
relative to the input reference. When the COAST signal is pre-
sented, the PLL maintains its output frequency in the absence
of HSYNC. A 32-step sampling phase adjustment is provided.
Data, HSYNC and Data Clock output phase relationships are
always maintained. The PLL can be disabled and an external
clock input provided as the pixel clock.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This device is fully program-
mable via a two-wire serial port.
Fabricated in an advanced CMOS process, the AD9884A is
provided in a space-saving 128-lead MQFP surface mount plastic
package and is specified over a 0°C to +70°C temperature range.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001






AD9884A Datasheet, Funktion
PIN CONFIGURATION
NC 1
NC 2
NC 3
VD 4
GND 5
GND 6
RAIN
VD
GND
7
8
9
VD 10
VD 11
GND 12
GND 13
SOGIN 14
GAIN
VD
GND
15
16
17
VD 18
VD 19
GND 20
GND 21
BAIN
VD
GND
22
23
24
VD 25
GND 26
CKINV 27
CLAMP 28
SDA 29
SCL 30
A0
A1
PVD
PVD
GND
31
32
33
34
35
NC 36
NC 37
NC 38
PIN 1
IDENTIFIER
AD9884A
TOP VIEW
PINS DOWN
(Not to Scale)
NC = NO CONNECT
AD9884A
102 DRB0
101 DRB1
100 DRB2
99 DRB3
98 DRB4
97 DRB5
96 DRB6
95 DRB7
94 VDD
93 GND
92 DGA0
91 DGA1
90 DGA2
89 DGA3
88 DGA4
87 DGA5
86 DGA6
85 DGA7
84 VDD
83 GND
82 DGB0
81 DGB1
80 DGB2
79 DGB3
78 DGB4
77 DGB5
76 DGB6
75 DGB7
74 VDD
73 GND
72 DBA0
71 DBA1
70 DBA2
69 DBA3
68 DBA4
67 DBA5
66 DBA6
65 DBA7
REV. C
–5–

6 Page









AD9884A pdf, datenblatt
AD9884A
GENERAL CONTROL
0A 7
DEMUX
Output Port Select
A bit that determines whether all pixels are presented to a single
port (A), or alternating pixels are demultiplexed to Ports A and B.
DEMUX
0
1
Function
All Data Goes to Port A
Alternate Pixels Go to Port A and Port B
When DEMUX = 0, Port B outputs are in a high impedance state.
The power-up default value is DEMUX = 1.
0A 6
PARALLEL Output Timing Select
Setting this bit to a Logic 1 delays data on Port A and the
DATACK output by one-half DATACK period so that the
rising edge of DATACK may be used to externally latch data
from both Port A and Port B. When this bit is set to a Logic 0,
the rising edge of DATACK may be used to externally latch
data from Port A only, and the DATACK rising edge may be
used to externally latch data from Port B.
PARALLEL
0
1
Function
Data Alternates Between Ports
Simultaneous Data on Alternate DATACKs
When in single port mode (DEMUX = 0), this bit is ignored.
The power-up default value is PARALLEL = 1.
0A 5
HSPOL
HSYNC Polarity
A bit that must be set to indicate the polarity of the HSYNC
signal that is applied to the HSYNC input.
HSPOL
0
1
Function
Active LOW
Active HIGH
Active LOW is the traditional negative-going HSYNC pulse.
Sampling timing is based on the leading edge of HSYNC, which
is the FALLING edge. The Clamp Position, as determined by
CLPLACE, is measured from the trailing edge.
Active HIGH is inverted from the traditional HSYNC, with a
positive-going pulse. This means that sampling timing will be
based on the leading edge of HSYNC, which is now the RISING
edge, and clamp placement will count from the FALLING edge.
The device will operate more-or-less properly if this bit is set
incorrectly, but the internally generated clamp position, as
established by CLPOS, will not be placed as expected, which
may generate clamping errors.
The power-up default value is HSPOL = 1.
0A 4
CSTPOL
COAST Polarity
A bit that must be set to indicate the polarity of the COAST
signal that is applied to the COAST input.
CSTPOL
0
1
Function
Active LOW
Active HIGH
Active LOW means that the clock generator will ignore HSYNC
inputs when COAST is LOW, and continue operating at the
same nominal frequency until COAST goes HIGH.
Active HIGH means that the clock generator will ignore HSYNC
inputs when COAST is HIGH, and continue operating at the
same nominal frequency until COAST goes LOW.
The power-up default value is CSTPOL = 1.
0A 3
EXTCLMP Clamp Signal Source
A bit that determines the source of clamp timing.
EXTCLMP
0
1
Function
Internally-generated clamp
Externally-provided clamp signal
A 0 enables the clamp timing circuitry controlled by CLPLACE
and CLDUR. The clamp position and duration is counted from
the trailing edge of HSYNC.
A 1 enables the external CLAMP input pin. The three channels
are clamped when the CLAMP signal is active. The polarity of
CLAMP is determined by the CLAMPOL bit.
The power-up default value is EXTCLMP = 0.
0A 2
CLAMPOL Clamp Signal Polarity
A bit that determines the polarity of the externally provided
CLAMP signal.
CLAMPOL
0
1
Function
Active LOW
Active HIGH
A 0 means that the circuit will clamp when CLAMP is LOW,
and it will pass the signal to the ADC when CLAMP is HIGH.
A 1 means that the circuit will clamp when CLAMP is HIGH,
and it will pass the signal to the ADC when CLAMP is LOW.
The power-up default value is CLAMPOL = 1.
0A 1
EXTCLK
External Clock Select
A bit that determines the source of the pixel clock.
EXTCLK
0
1
Function
Internally generated clock
Externally provided clock signal
A 0 enables the internal PLL that generates the pixel clock from
an externally-provided HSYNC.
A 1 enables the external CKEXT input pin. In this mode, the
PLL Divide Ratio (PLLDIV) is ignored. The clock phase adjust
(PHASE) is still functional.
The power-up default value is EXTCLK = 0.
REV. C
–11–

12 Page





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