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PDF AD9883A Data sheet ( Hoja de datos )
| Número de pieza | AD9883A | |
| Descripción | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Industrial Temperature Range Operation
140 MSPS Maximum Conversion Rate
300 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 110 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for Hot Plugging
Midscale Clamping
Power-Down Mode
Low Power: 500 mW Typical
4:2:2 Output Format Mode
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TV
110 MSPS/140 MSPS Analog Interface
for Flat Panel Displays
AD9883A
FUNCTIONAL BLOCK DIAGRAM
RAIN
GAIN
BAIN
HSYNC
COAST
CLAMP
FILT
SCL
SDA
A0
CLAMP
8
A/D
ROUTA
CLAMP
8
A/D
GOUTA
CLAMP
8
A/D
SYNC
PROCESSING
AND CLOCK
GENERATION
SERIAL REGISTER
AND
POWER MANAGEMENT
REF
AD9883A
BOUTA
MIDSCV
DTACK
HSOUT
VSOUT
SOGOUT
REF
BYPASS
GENERAL DESCRIPTION
The AD9883A is a complete 8-bit, 140 MSPS, monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280 × 1024 at 75 Hz).
The AD9883A includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and Hsync and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883A’s on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz to
140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9883A also offers full sync
processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883A is pro-
vided in a space-saving 80-lead LQFP surface-mount plastic package
and is specified over the –40°C to +85°C temperature range.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
Parameter
Test
AD9883ABST–110
Temp Level Min Typ
Max
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
PVD Supply Voltage
ID Supply Current (VD)
IDD Supply Current (VDD)2
IPVD Supply Current (PVD)
Total Power Dissipation
Power-Down Supply Current
Power-Down Dissipation
Full
Full
Full
25°C
25°C
25°C
Full
Full
Full
IV
IV
IV
V
V
V
VI
VI
VI
3.0
2.2
3.0
3.3
3.3
3.3
132
19
8
525
5
16.5
3.6
3.6
3.6
700
15
33
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 40.7 MHz
Crosstalk
25°C
25°C
25°C
25°C
Full
Full
V
V
V
V
V
V
300
2
1.5
44
43
55
THERMAL CHARACTERISTICS
θJC Junction-to-Case
Thermal Resistance
V
θJA Junction-to-Ambient
Thermal Resistance
V
16
35
NOTES
1VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693.
2DATACK Load = 15 pF, Data Load = 5 pF.
Specifications subject to change without notice.
AD9883A
AD9883ABST–140
Min Typ Max
Unit
3.0 3.3 3.6
2.2 3.3 3.6
3.0 3.3 3.6
163
24
10
650 850
5 15
16.5 33
V
V
V
mA
mA
mA
mW
mA
mW
300 MHz
2 ns
1.5 ns
43 dB
42 dB
55 dBc
16
°C/W
35
°C/W
REV. B
–5–
5 Page 
AD9883A
OFFSET = 7FH
OFFSET = 3FH
1.0
OFFSET = 00H
0.5
OFFSET = 7FH
OFFSET = 3FH
0.
0
OFFSET = 00H
00H FFH
GAIN
Figure 2. Gain and Offset Control
Gain and Offset Control
The AD9883A can accommodate input signals with inputs
ranging from 0.5 V to 1.0 V full scale. The full-scale range is set
in three 8-bit registers (Red Gain, Green Gain, and Blue Gain).
Note that increasing the gain setting results in an image with
less contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (Red Offset,
Green Offset, Blue Offset) provide independent settings for
each channel. The offset controls provide a ± 63 LSB adjust-
ment range. This range is connected with the full-scale range, so
if the input range is doubled (from 0.5 V to 1.0 V) then the offset
step size is also doubled (from 2 mV per step to 4 mV per step).
Figure 2 illustrates the interaction of gain and offset controls.
The magnitude of an LSB in offset adjustment is proportional
to the full-scale range, so changing the full-scale range also
changes the offset. The change is minimal if the offset setting is
near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same amount
as the zero scale level.
Sync-on-Green
The Sync-on-Green input operates in two steps. First, it sets a
baseline clamp level off of the incoming video signal with a
negative peak detector. Second, it sets the sync trigger level to a
programmable level (typically 150 mV) above the negative peak.
The Sync-on-Green input must be ac-coupled to the Green
analog input through its own capacitor, as shown in Figure 3.
The value of the capacitor must be 1 nF ± 20%. If Sync-on-Green
is not used, this connection is not required. Note that the Sync-
on-Green signal is always negative polarity.
Clock Generation
A phase locked loop (PLL) is employed to generate the pixel
clock. In this PLL, the Hsync input provides a reference fre-
quency. A voltage controlled oscillator (VCO) generates a much
higher pixel clock frequency. This pixel clock is divided by the
PLL divide value (registers 01H and 02H) and phase compared
with the Hsync input. Any error is used to shift the VCO fre-
quency and maintain lock between the two signals.
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,
there is a period during which the signal is slewing from the old
pixel amplitude and settling at its new value. Then there is a
time when the input voltage is stable, before the signal must
slew to a new value (Figure 4). The ratio of the slewing time to
the stable time is a function of the bandwidth of the graphics
DAC and the bandwidth of the transmission system (cable and
termination). It is also a function of the overall pixel rate. Clearly,
if the dynamic characteristics of the system remain fixed, the
slewing and settling time is likewise fixed. This time must be
subtracted from the total pixel period, leaving the stable period.
At higher pixel frequencies, the total cycle time is shorter, and the
stable pixel time becomes shorter as well.
PIXEL CLOCK
INVALID SAMPLE TIMES
Figure 4. Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined, and must also be subtracted
from the stable pixel time.
Considerable care has been taken in the design of the AD9883A’s
clock generation circuit to minimize jitter. As indicated in
Figure 5, the clock jitter of the AD9883A is less than 5% of the
total pixel time in all operating modes, making the reduction in
the valid sampling time due to jitter negligible.
14
12
47nF
47nF
47nF
1nF
RAIN
BAIN
GAIN
SOG
Figure 3. Typical Clamp Configuration
10
8
6
4
2
REV. B
–11–
0
0 31.5 36.0 36.0 50.0 56.25
75.0 85.5
FREQUENCY – MHz
110.0
Figure 5. Pixel Clock Jitter vs. Frequency
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD9883A.PDF ] | |
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