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AD9883 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9883
Beschreibung 110 MSPS Analog Interface for Flat Panel Displays
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD9883 Datasheet, Funktion
a
FEATURES
110 MSPS Maximum Conversion Rate
300 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 110 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for ”Hot Plugging”
Midscale Clamping
Power-Down Mode
Low Power: 500 mW Typical
Composite Sync Applications Require an External Coast
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TV
110 MSPS Analog Interface for
Flat Panel Displays
AD9883
FUNCTIONAL BLOCK DIAGRAM
RAIN
GAIN
BAIN
HSYNC
COAST
CLAMP
FILT
SCL
SDA
A0
CLAMP
8
A/D
ROUTA
CLAMP
8
A/D
GOUTA
CLAMP
8
A/D
SYNC
PROCESSING
AND CLOCK
GENERATION
SERIAL REGISTER
AND
POWER MANAGEMENT
REF
AD9883
BOUTA
MIDSCV
DTACK
HSOUT
VSOUT
SOGOUT
REF
BYPASS
GENERAL DESCRIPTION
The AD9883 is a complete 8-bit, 110 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 110 MSPS encode
rate capability and full-power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280 × 1024 at 60 Hz).
The AD9883 includes a 110 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and HSYNC and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883’s on-chip PLL generates a pixel clock from HSYNC
and COAST inputs. Pixel clock output frequencies range from
12 MHz to 110 MHz. PLL clock jitter is 500 ps p-p typical at
110 MSPS. When the COAST signal is presented, the PLL
maintains its output frequency in the absence of HSYNC. A
sampling phase adjustment is provided. Data, HSYNC and
Clock output phase relationships are maintained. The AD9883
also offers full sync processing for composite sync and sync-on-
green applications.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This interface is fully pro-
grammable via a two-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883 is
provided in a space-saving 80-lead LQFP surface mount plastic
package and is specified over the 0°C to 70°C temperature range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001






AD9883 Datasheet, Funktion
AD9883
PIN FUNCTION DETAIL
Outputs
HSOUT
Horizontal Sync Output
A reconstructed and phase-aligned version of
the Hsync input. Both the polarity and dura-
tion of this output can be programmed via
serial bus registers.
By maintaining alignment with DATACK,
and Data, data timing with respect to horizon-
tal sync can always be determined.
VSOUT
Vertical Sync Output
A reconstructed and phase-aligned version of
the video Vsync. The polarity of this output
can be controlled via a serial bus bit. The place-
ment and duration in all modes is set by the
graphics transmitter.
SOGOUT
Sync On Green Slicer Output
This pin outputs either the signal from the
Sync-On-Green slicer comparator or an unproc-
essed but delayed version of the Hsync input.
See the Sync Block Diagram (Figure 11) to
view how this pin is connected.
(Note: Besides slicing off SOG, the output from
this pin gets no other additional processing on
the AD9883. Vsync separation is performed via
the sync separator.)
Serial Port
(Two-Wire)
SDA
SCL
A0
Serial Port Data I/O
Serial Port Data Clock
Serial Port Address Input 1
For a full description of the two-wire serial
register and how it works, refer to the Two-
Wire Serial Control Port section.
Data Outputs
RED
GREEN
BLUE
Data Output, Red Channel
Data Output, Green Channel
Data Output, Blue Channel
The main data outputs. Bit 7 is the MSB. The
delay from pixel sampling time to output is
fixed. When the sampling time is changed by
adjusting the PHASE register, the output timing
is shifted as well. The DATACK and HSOUT
outputs are also moved, so the timing rela-
tionship among the signals is maintained. For
exact timing information, refer to Figures 7
and 8.
Data Clock
Output
DATACK
Data Output Clock
This is the main clock output signal used to
strobe the output data and HSOUT into
external logic.
It is produced by the internal clock generator
and is synchronous with the internal pixel
sampling clock.
Inputs
RAIN
GAIN
BAIN
HSYNC
VSYNC
SOGIN
–6–
When the sampling time is changed by adjust-
ing the PHASE register, the output timing is
shifted as well. The Data, DATACK, and
HSOUT outputs are all moved, so the timing
relationship among the signals is maintained.
Analog Input for RED Channel
Analog Input for GREEN Channel
Analog Input for BLUE Channel
High-impedance inputs that accept the RED,
GREEN, and BLUE channel graphics signals,
respectively. (The three channels are identical,
and can be used for any colors, but colors are
assigned for convenient reference.)
They accommodate input signals ranging from
0.5 V to 1.0 V full scale. Signals should be
ac-coupled to these pins to support clamp
operation.
Horizontal Sync Input
This input receives a logic signal that estab-
lishes the horizontal timing reference and
provides the frequency reference for pixel
clock generation.
The logic sense of this pin is controlled by
serial register 0Eh Bit 6 (Hsync Polarity). Only
the leading edge of Hsync is active, the trailing
edge is ignored. When Hsync Polarity = 0, the
falling edge of Hsync is used. When Hsync
Polarity = 1, the rising edge is active.
The input includes a Schmitt trigger for noise
immunity, with a nominal input threshold
of 1.5 V.
Vertical Sync Input
This is the input for vertical sync.
Sync-on-Green Input
This input is provided to assist with processing
signals with embedded sync, typically on the
GREEN channel. The pin is connected to a
high-speed comparator with an internally gener-
ated threshold. The threshold level can be
programmed in 10 mV steps to any voltage
between 10 mV and 330 mV above the negative
peak of the input signal. The default voltage
threshold is 150 mV.
When connected to an ac-coupled graphics
signal with embedded sync, it will produce
a noninverting digital output on SOGOUT.
(This is usually a composite sync signal, contain-
ing both vertical and horizontal sync information
that must be separated before passing the hori-
zontal sync signal to Hsync.)
When not used, this input should be left uncon-
nected. For more details on this function and
how it should be configured, refer to the Sync
on Green section.
REV. 0

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AD9883 pdf, datenblatt
AD9883
Coast Timing
In most computer systems, the Hsync signal is provided con-
tinuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary, and should not be used and
the pin should be permanently connected to the inactive state.
In some systems, however, Hsync is disturbed during the
Vertical Sync period (Vsync). In some cases, Hsync pulses
disappear. In other systems, such as those that employ Compos-
ite Sync (Csync) signals or embedded Sync-On-Green (SOG),
Hsync includes equalization pulses or other distortions during
Vsync. To avoid upsetting the clock generator during Vsync,
it is important to ignore these distortions. If the pixel clock
PLL sees extraneous pulses, it will attempt to lock to this new
frequency, and will have changed frequency by the end of the
Vsync period. It will then take a few lines of correct Hsync tim-
ing to recover at the beginning of a new frame, resulting in a
“tearing” of the image at the top of the display.
The COAST input is provided to eliminate this problem. It is
an asynchronous input that disables the PLL input and allows
the clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
–12–
REV. 0

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