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PDF AD9882 Data sheet ( Hoja de datos )
| Número de pieza | AD9882 | |
| Descripción | Dual Interface for Flat Panel Displays | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9882 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Dual Interface for
Flat Panel Displays
AD9882
FEATURES
Analog Interface
140 MSPS Maximum Conversion Rate
Programmable Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamping
4:2:2 Output Format Mode
Digital Interface
DVI 1.0 Compatible Interface
112 MHz Operation
High Skew Tolerance of 1 Full Input Clock
Sync Detect for “Hot Plugging”
Supports High Bandwidth Digital Content Protection
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converter
Microdisplays
Digital TV
GENERAL DESCRIPTION
The AD9882 offers designers the flexibility of an analog interface
and Digital Visual Interface (DVI) receiver integrated on a single
chip. Also included is support for High bandwidth Digital
Content Protection (HDCP).
Analog Interface
The AD9882 is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280 ¥ 1024 at 75 Hz).
The analog interface includes a 140 MHz triple ADC with
internal 1.25 V reference, a Phase Locked Loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only a 3.3 V power supply, analog input, and Hsync. Three-
state CMOS outputs may be powered from 2.2 V to 3.3 V.
The AD9882’s on-chip PLL generates a pixel clock from Hsync.
Pixel clock output frequencies range from 12 MHz to 140 MHz.
PLL clock jitter is typically 500 ps p-p at 140 MSPS. The AD9882
also offers full sync processing for composite sync and Sync-on-
Green (SOG) applications.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
FUNCTIONAL BLOCK DIAGRAM
RAIN
GAIN
BAIN
SOGIN
HSYNC
FILT
VSYNC
AD9882
ANALOG INTERFACE
REF
CLAMP
A/D 8 ROUT
CLAMP
A/D 8 GOUT
CLAMP
A/D 8 BOUT
SYNC
PROCESSING AND
CLOCK
GENERATION
DATACK
HSOUT
VSOUT
SOGOUT
8
8
8
SCL
SDA
A0
SERIAL REGISTER AND
POWER MANAGEMENT
MUXES
RX0+
RX0–
RX1+
RX1–
RX2+
RX2–
RXC+
RXC–
RTERM
DDCSCL
DDCSDA
MCL
MDA
DIGITAL INTERFACE
DVI
RECEIVER
8
8
8
HDCP
ROUT
GOUT
BOUT
DATACK
DE
HSYNC
VSYNC
REFBYPASS
ROUT
GOUT
BOUT
DATACK
HSOUT
VSOUT
SOGOUT
DE
Digital Interface
The AD9882 contains a DVI 1.0 compatible receiver and supports
display resolutions up to SXGA (1280 ¥ 1024 at 60 Hz). The
receiver features an intra-pair skew tolerance of up to one full
clock cycle.
With the inclusion of HDCP, displays may now receive encrypted
video content. The AD9882 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and renew-
ability of that authentication during transmission as specified by
the HDCP v1.0 protocol.
Fabricated in an advanced CMOS process, the AD9882 is
provided in a space-saving 100-lead LQFP surface-mount plastic
package and is specified over the 0∞C to 70∞C temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
AD9882
Parameter
AC SPECIFICATIONS
Intra-Pair (+ to –) Differential
Input Skew (TDPS)
Channel-to-Channel Differential
Input Skew (TCCS)
Low-to-High Transition Time
for Data (DLHT)
Conditions
Test
Temp Level
Full IV
Full IV
Output Drive = High,
CL = 10 pF
Output Drive = Med,
CL = 7 pF
Output Drive = Low,
CL = 5 pF
Full
Full
Full
IV
IV
IV
Low-to-High Transition Time for
DATACK (DLHT)
Output Drive = High,
CL = 10 pF
Output Drive = Med,
CL = 7 pF
Output Drive = Low,
CL = 5 pF
Full
Full
Full
IV
IV
IV
High-to-Low Transition Time for
Data (DHLT)
Output Drive = High,
CL = 10 pF
Output Drive = Med,
CL = 7 pF
Output Drive = Low,
CL = 5 pF
Full
Full
Full
IV
IV
IV
High-to-Low Transition Time for
DATACK (DHLT)
Data-to-Clock Skew4
Duty Cycle, DATACK4
DATACK Frequency (FCIP)
Output Drive = High,
CL = 10 pF
Output Drive = Med,
CL = 7 pF
Output Drive = Low,
CL = 5 pF
Full
Full
Full
Full
Full
Full
NOTES
1The typical pattern contains a grayscale area, Output Drive = High.
2DATACK Load = 10 pF, Data Load = 10 pF.
3The worst-case pattern contains a black and white checkerboard pattern, Output Drive = High.
4DRIVE STRENGTH = 11
Specifications subject to change without notice.
IV
IV
IV
IV
IV
VI
AD9882KST
Min Typ Max
360
1
2.2
2.5
3.2
1.0
1.6
2.1
2.2
1.9
1.7
1.0
1.0
1.4
–0.5 +2.0
40 46 50
25 112
Unit
ps
Clock
Period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
MHz
REV. A
–5–
5 Page 
RED
GREEN
BLUE
Data Output, RED Channel
Data Output, GREEN Channel
Data Output, BLUE Channel
These are the main data outputs. Bit 7 is the MSB.
The delay from pixel sampling time to output is
fixed. When the sampling time is changed by
adjusting the PHASE register, the output timing
is shifted as well. The DATACK and HSOUT
outputs are also moved, so the timing relation-
ship among the signals is maintained.
Please refer to the timing diagrams for more
information.
VDD
PVD
POWER SUPPLY
VD Main Power Supply
These pins supply power to the main elements of
the circuit. They should be as quiet as possible.
GND
AD9882
Digital Output Power Supply
A large number of output pins (up to 25) switch-
ing at high speed (up to 140 MHz) generates a
lot of power supply transients. These supply
pins are identified separately from the VD pins
so special care can be taken to minimize out-
put noise transferred into the sensitive analog
circuitry.
If the AD9882 is interfacing with lower voltage
logic, VDD may be connected to a lower supply
voltage (as low as 2.2 V) for compatibility.
Clock Generator Power Supply
The most sensitive portion of the AD9882 is the
clock generation circuitry. These pins provide
power to the clock PLL and help the user design
for optimal performance. The designer should
provide noise-free power to these pins.
Ground
The ground return for all circuitry on chip. It is
recommended that the AD9882 be assembled on
a single solid ground plane, with careful attention
to ground current paths.
AIO
(0FH Bit 2)
1
0
Analog
Interface
Detect
X
0
0
1
1
Digital
Interface
Detect
X
0
1
0
1
Table III. Interface Selection Controls
AIS
(0FH Bit 1)
0
1
X
X
X
0
1
Active
Interface
Analog
Digital
None
Digital
Analog
Analog
Digital
Description
Force the analog interface active.
Force the digital interface active.
Neither interface was detected. Both interfaces are
powered down.
The digital interface was detected. Power down the
analog interface.
The analog interface was detected. Power down the
digital interface.
Both interfaces were detected. The analog interface
gets priority.
Both interfaces were detected. The digital interface
gets priority.
REV. A
–11–
11 Page | ||
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| PDF Descargar | [ Datasheet AD9882.PDF ] | |
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